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The RISC-V Vector extension (RVV) enables processor cores based on the RISC-V instruction set architecture to process data arrays, alongside traditional scalar operations to accelerate the computation of single instruction streams on large data sets. The RISC-V International vector working group is ...

OpenFive is a solution-centric and processor agnostic custom silicon business unit dedicated to building optimized domain-specific SoCs Today, I am excited to announce the launch of OpenFive, a self-contained and autonomous custom silicon business unit of SiFive, Inc. OpenFive is solution-centric an...

SiFive's Best Processor Portfolio Is Here We’re pleased to announce a comprehensive update to SiFive’s RISC-V IP Portfolio with the SiFive 20G1 release. This release brings important enhancements and new capabilities to SiFive Core IP, the industry's broadest RISC-V IP Portfolio, ranging from the ul...

The SiFive Mission SiFive’s mission is to accelerate chip design, closing the time between the definition of a chip to silicon being available - we call this the ‘idea to silicon' journey. The solutions to modern computing challenges increasingly require domain-specific accelerators, silicon chips d...

Access, Observe, Control The term ‘debug’ has a storied history. It’s widely reported as being coined by computing pioneer, US Navy Rear Admiral Grace Hopper, when she removed a moth from Harvard’s Mark II computer in 1945. Use of the word bug can also be traced to the great inventor, Thomas Edison,...

As part of our ongoing effort to spread knowledge about the RISC-V ISA around the globe, we hosted a two-day long RISC-V Symposium/Workshop in the ancient city of Ahmedabad, India. The event was co-hosted by Nirma University at their campus at Ahmedabad. The first day of the event was the symposium ...