Published by SemiWiki. Before the advent of RISC-V, designers looking for embedded processors were effectively limited to a handful of proprietary processors using ISAs from decades ago. While the major ISAs are being updated and enhanced, they also are facing limitations from many decisions made ov...

A Platform Designed for Continued Engagement with the Global Hardware and Software Community Developing RISC-V Based Semiconductor Solutions. After hosting the SiFive Tech Symposiums in a record 52 cities in 2019, it became amply evident that the RISC-V revolution has reached all corners of the glob...

The SiFive Mission SiFive’s mission is to accelerate chip design, closing the time between the definition of a chip to silicon being available - we call this the ‘idea to silicon' journey. The solutions to modern computing challenges increasingly require domain-specific accelerators, silicon chips d...

Access, Observe, Control The term ‘debug’ has a storied history. It’s widely reported as being coined by computing pioneer, US Navy Rear Admiral Grace Hopper, when she removed a moth from Harvard’s Mark II computer in 1945. Use of the word bug can also be traced to the great inventor, Thomas Edison,...

As part of our ongoing effort to spread knowledge about the RISC-V ISA around the globe, we hosted a two-day long RISC-V Symposium/Workshop in the ancient city of Ahmedabad, India. The event was co-hosted by Nirma University at their campus at Ahmedabad. The first day of the event was the symposium ...

Our SiFive Tech Symposiums in San José, Costa Rica and Mexico City, Mexico were well attended by not only those in industry, but in academia as well. There is a great deal of enthusiasm and engagement in RISC-V in both of these regions. Many new friendships were formed, and we look forward to the co...