SiFive - June 01, 2022

10 Important Things To Know About SiFive Vectors

A great way to get to know more about popular SiFive vector processors, which are compatible with the RISC-V Vector (RVV) version 1.0 specification

1.) The RISC-V Vector (RVV) ISA was ratified at version 1.0 by RISC-V International in December of 2021 but it’s fair to say it’s been a big part of the SiFive and RISC-V journey and was being contemplated by the original inventors of RISC-V, namely Krste Asanovic, Andrew Waterman and Yunsup Lee, right from the beginning of the inception of RISC-V at UC Berkeley back in 2015. In fact, Krste was actually working with vectors and developing vector processors as part of his Ph.D back in the late 90s . In one of his talks about the history of RISC-V Vectors, Krste explains that there is a running joke that the V in RISC-V secretly stands for vectors.

2.) One of the key defining features of the RISC-V Vector ISA is that it is vector length agnostic. This means that software code that has been written for any RISC-V vector compliant processor will work on any other RISC-V vector processor. From a software reuse perspective, this has a huge reward with many benefits; imagine the case where a first-generation end-product was designed around a 256-bit length vector register processor, for example, the SiFive® Performance™ P270, due to it having the perfect balance of power, performance, and area for that first design. As the product gained market success, new requirements evolved for the second generation product resulting in improved performance from the longer vector register length processor, for example, the SiFive Intelligence™ X280 with its 512-bit length vector registers. In this situation not only will the software code execute directly on the X280, but the code performance will improve immensely, without having to change even one line of code. This results in much-reduced design and development time, therefore a much faster time to market for the second generation product, with a very appealing faster time to revenue.

3.) The RISC-V Vector ISA is a very clean and optimized set of instructions, with the base ISA numbering around just 300 instructions, far smaller than a typical packed-SIMD alternative. Crucially these powerful instructions can each do a lot of work. The key benefits this brings are two-fold in that,

  • as instruction codings take up area in a chip, this area is decreased
  • compilers generate very dense code, reducing the area needed for code storage

By minimizing this area overhead this ultimately leads to better power efficiency with a smaller memory footprint. This tutorial video, while recorded prior to the final ratification of the specification, gives a great amount of detail on the overall vector ISA and explains the design philosophy and why RISC-V Vectors is considered “The best vector ISA ever!”

4.) RVV evolved to where it is today as a powerful and more efficient (in code size, performance, and area) alternative to the inefficient use of packed-SIMD and GPUs for the processing of large datasets. From its inception one of the biggest drivers was that the ISA was efficient and scalable to all reasonable design points. This meant being equally as applicable to both low-cost designs as to the highest performance applications. For this reason the ISA needed to be able to support in-order, decoupled, or out-of-order microarchitectures, along with integer, fixed-point and/or floating point data types. In a RISC-V workshop talk in 2015, Krste further explains additional design considerations for the RISC-V Vector extension as:

  • being a great compiler target
  • supporting both implicit auto-vectorization and explicit programming models
  • able to work with virtualization layers
  • fit into standard fixed 32-bit encoding space
  • be a base for future vector extensions

Importantly, the design considerations were also to not replicate or be like a GPU or packed-SIMD implementation. Krste also explains some of the problems with packed-SIMD and GPU implementations, explaining how they can lead to multiple new instructions being required, therefore chip size increases, (as new data types are introduced) but also additional code required for lots of corner case handling, increasing code size (therefore bill of materials (BOM) cost), along with requiring more power.

5.) If you have existing products and software utilizing packed-SIMD code, did you know that SiFive has tools to easily port your code to RISC-V vectors? SiFive Recode can easily take code designed and written for packed-SIMD implementations and port to SiFive vectors. Additionally, for new application code, we have been very active in the open source community to offer an LLVM-based auto-vectorizing compiler, to enable faster time to market.

6.) As modern workloads have evolved, more complex systems have been designed with customized accelerators such as DSPs (digital signal processors) and simple finite state machines (FSM), so as to offer the best performance for specific application workloads and algorithms. Whilst the performance gain can be impressive there are a number of shortfalls to this situation:

  • there can be increased power and chip area due to the need for the accelerator to match the speed of the main processor by implementing a cache system
  • the accelerator may require a separate toolchain with associated increased software complexity (and potentially software design time)

The X280 enables consolidation of custom accelerators and control processors, resulting in a more power efficient solution and ease of use and programmability, with standard software and out-of-the-the box open source toolchains.

7.) "Standard software" - two very important words to a software developer when working on complex designs. RVV is an open standard and much of the code written for RVV will be available in the open source domain. This allows developers to access the large and growing ecosystem of RVV-based algorithms, along with access to a full range of open source and commercial grade tools for compilation, modeling, debug and trace. The upside and key benefits of this are:

  • access to open source algorithms
  • standardized and stable approach to algorithm development
  • reduced development costs
  • and crucially, enabling much faster time to market

8.) RVV includes a broad range of data types; including floating point, integer, and fixed point that are efficiently executed on the same single Vector ALU; this simplifies the processor architecture, resulting in improved power efficiency and reduced chip area.

9.) SiFive has a strong customer base for its vector-based product line - in fact, it is one of the fastest licensed IP product lines. Following the 2021 release of the SiFive Performance P270 and SiFive Intelligence X280 processors, we have worked with customers to define a roadmap that adds some powerful new features and enhancements, higher performance vector-based processors, along with wider vector registers - watch out for more vector-based products throughout 2022 and beyond. If you want to find out more about licensing the P270 or X280 then please contact us for more details.

10.) Finally, if Vectors is your thing and you’re craving to be part of the growing teams across the globe building the next generation of products from SiFive then get in touch. We have some great career opportunities in the USA, Taiwan, France, and in the UK. Check out the SiFive Careers page for all of the latest updates.

Want to learn more? Contact us or access the other materials on our SiFive vectors page

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