- Up to 16 hardware breakpoints for precise control
- Up to 16 external triggers, allowing cores to be halted or resumed by external events
Trace and Debug
Bring up first silicon, test and debug software with a comprehensive, pre-integrated advanced trace and debug solution for RISC-V processors standalone or with industry leading tool vendors

SiFive Advanced Trace & Debug
The Ultimate RISC‑V Debugging Solution
Elevate your development process with SiFive Insight, a comprehensive portfolio of trace and debug IP, software, and tools designed to simplify and accelerate the creation of SiFive RISC-V products. With SiFive Insight, you gain unparalleled visibility and control over your design, making the debugging process seamless and efficient.
SiFive Insight Standard Debug: Simplify Your Debugging
SiFive Insight Standard Debug is included with all SiFive Core IP licenses and provides essential debugging capabilities for your RISC‑V design and is easily configured using SiFive Core Designer. It offers Run-Control debug via an external port compliant with RISC-V Debug Spec v0.14, with options for:
- JTAG
- 2-Wire cJTAG
- Arm® CoreSight™–compliant AMBA® APB
The CoreSight-compliant APB interface enables debugging SiFive RISC-V cores alongside ARM processors using a single probe.

Key Features
- System Bus Access (SBA), for real-time debugging without interrupting the core
- Performance Counters for in-depth timing and performance metrics (up to 8 selectable counters)
SiFive Insight Advanced Trace & Debug: Advanced Visibility
For more advanced debugging and trace capabilities, the SiFive Insight Advanced Trace and Debug option integrates the Nexus 5001–compliant Trace Encoder. This powerful component efficiently encodes executed addresses and opcodes from the core into a format usable by tools to reconstruct execution history.
Advanced Trace Features
- Configurable Trace Output:
Direct trace data to:
SRAM
ATB - Advanced Trace Bus
SWT - Serial Wire Trace
SBA – System Bus Access
PIB – Probe Interface Block - Compression Options: Choose between Branch Taken Messages (BTMs) or History Trace Messages (HTMs) for optimized trace data storage
- Timestamping: Available in 40, 48, or 56-bit widths to measure the duration between various events
- External Triggers: Program up to 8 inputs and outputs for start/stop trace and trace sync insertion
- Multi-Core Support: Includes a trace funnel to aggregate data from multi-core clusters, allowing precise trace separation per core
Instrumented Trace Component (ITC)
The ITC provides 16 unique 32-bit stimulus registers, offering extensive instrumentation options for your code.
Key features include:
- Printf over trace
- Task ID recording
- Precise execution timings with hardware timestamps
PC Sampling for Hot-Spot Analysis
Capture real-time execution data with PC Sampling. This feature monitors the program counter while the core is running and is instrumental in pinpointing execution hot-spots. It also supports Crash Recovery by capturing the last PC before a system crash, providing insights into the code running at the time of failure.
IDE Integration
SiFive Insight’s advanced debugging capabilities are fully integrated into SiFive Freedom Studio, a cross-platform IDE based on Eclipse. With support for Linux, Windows, and macOS, Freedom Studio offers a complete debugging environment with features such as:
- Trace view with source and assembly code
- Execution hot-spot viewer for performance insights
- Live Variables for up-to-date variable values
- Performance counter setup and viewing
- State browser for detailed system exploration
3rd Party Debug Integration
SiFive Insight is compatible with leading third-party debug solutions, providing seamless integration with industry-standard IDEs, including:
- Ashling
- IAR
- Lauterbach
- Segger
With SiFive Insight Advanced Trace & Debug, you get unmatched debugging power and flexibility, ensuring you can optimize your RISC-V design and speed up your development process.
Ready to elevate your RISC-V development?
Explore SiFive Insight today and unlock the full potential of your SiFive RISC-V cores.