RISC-V for Infrastructure: For Now, It’s All About the Developer

By Ian Ferguson, V.P. of Business Development, SiFive

When I joined SiFive in early 2024, the initial focus (which has since broadened) was to explore how best to drive adoption of SiFive’s RISC-V technology into system-on-chip components targeting data center use cases. Efforts to introduce new technologies, and to displace long-term incumbents, are not initiatives that succeed in just a few quarters. These programs take years to execute. I speak from experience: in early 2008, a few colleagues and I, described internally as “rogues” (though we preferred “visionaries”), started the initiative to drive Arm into the server market.

Upon arriving at SiFive, it was clear that our CPU roadmap would, over time, catch up with the single-thread performance capabilities of products from incumbent suppliers. But three other areas also needed to be addressed to truly open this market to a broader set of customers, beyond just one or two early innovators.

The first area I’ll explore in this blog post is enabling the software developer community. I’ll leave the other two as a mystery (for now) and return to them in future posts later this year.

Three Numbers for You:

90

4

12,800

What do these numbers mean? Today, projections show that NVIDIA “owns” 90% of GPU-based neural network training. They boast a developer base exceeding four million people. And, on average, 12,800 lines of code are added, modified, or deleted in the Linux kernel each day.

A few folks have posited that "hardware is cool again," but fundamentally, without strong software support, the effort for companies to adopt new hardware technologies is simply too great.

In May, Red Hat announced the release of a developer edition of Red Hat Enterprise Linux (RHEL) for use on SiFive’s latest RISC-V developer board, the HiFive Premier P550. Alongside this, they also made RISC-V source code available for the CentOS community.

Then in July 2025, NVIDIA announced it is porting CUDA to RISC-V, using the HiFive Premier P550 as the starting point for this work. While no timeline was shared for when the code will be available, the announcement has already generated significant interest across the press, customer base, and competitor landscape.

At this point, I can’t expand beyond what’s already in the public domain. But there's an excellent analysis by Joe Byrne posted here that gives helpful context. As Joe writes:

“NVIDIA is making RISC-V a supported architecture, alongside Arm and x86—which means that, once the code is available, companies will be able to select a RISC-V CPU to be coupled alongside a NVIDIA GPGPU.”

RISC-V International also just released a blog based on a discussion with Frans Sijstermans, the NVIDIA executive who revealed the news at the RISC-V Summit China.

Common Themes from Red Hat and NVIDIA

I see three common threads across Red Hat’s and NVIDIA’s announcements:

Future-Readiness: Both companies are preparing for a future where RISC-V server hardware is widely deployed. They want to be ready for that reality.

Platform of Choice: Both are basing their initial work on the HiFive Premier P550 board. I believe that’s due to its high performance relative to other RISC-V boards, its stability, and the excellent work our engineering team is doing to upstream open source code—plus the performance and expansion capabilities of the hardware. Having this powerful capability in silicon is enabling many developers to get “hands-on” with RISC-V in new ways.

RVA23 Milestone: The ratification of the RVA23 profile has had a galvanizing effect. Large ecosystem players want to target platforms that are supported by multiple vendors with a consistent processor architecture. A common instruction set that software can count on is key to making that possible.

It would be remiss not to recognize the pioneering work Canonical has done in the RISC-V ecosystem—making Ubuntu a first-class citizen for RISC-V.

The combined investments of these industry heavyweights, along with support from many companies participating in the RISE Project, are bringing us closer to a reality where customers can choose among three processor architectures. Barriers for system builders, software developers, and component vendors are being removed—almost daily.

RISC-V is unique in its openness. Vendors can build chips for narrow, highly specialized vertical markets. NVIDIA clearly sees an opportunity here to extend CUDA into entirely new domains—something that would be much harder to do with other commercial ISAs designed to serve broad, generic markets.

The power of CUDA combined with the unlimited future of RISC-V is truly exciting.

SiFive recently celebrated our ten-year anniversary, and we continue to push the boundaries of what’s possible with RISC-V. As always, we want to hear from you—your ideas, your innovations, and your challenges.

We’ll all come together at the RISC-V Summit in Santa Clara this October, where I’m looking forward to some great presentations and discussions. Let’s use that as a platform to expand the conversation and accelerate momentum even further.

Ultimately, it’s now up to the RISC-V community to prove NVIDIA right.