资源与支持

SiFive 博客

来自 RISC-V 专家的最新洞察与深度技术解析

March 04, 2020

The RISC-V Revolution is Going Strong in Ahmedabad

As part of our ongoing effort to spread knowledge about the RISC-V ISA around the globe, we hosted a two-day long RISC-V Symposium/Workshop in the ancient city of Ahmedabad, India. The event was co-hosted by Nirma University at their campus at Ahmedabad.

The first day of the event was the symposium portion, and it was attended by students of various universities, research scholars, and many prominent industrial experts from Ahmedabad. Anand Bariya, VP of engineering at SiFive, delivered a keynote presentation that outlined the importance of the RISC-V ISA and SiFive’s role in advancing the open-source ecosystem. Another keynote was presented by Professor Usha Mehta of Nirma University, Ahmedabad, who spoke on the research activities currently taking place at the university. Rajesh Varadharajan, the director of IP engineering at SiFive, presented on RISC-V core IP for target vertical markets and software ecosystems, and also provided a tutorial on SiFive’s Core Designer. Approximately 160 people participated in the symposium.

The second day of this two-day event was a hands-on workshop where attendees were given the opportunity to practice what they learned on the previous day. All the participants were very enthusiastic to implement the RISC-V ISA and boot their program on an FPGA board. Approximately 130 people participated in the workshop, as the seats were limited. The experience in Ahmedabad was very rewarding. The enthusiasm of the participants from various backgrounds made it a great success! We’re very thankful to the management and staff of Nirma University for their gracious support and for co-hosting the event!

Glimpses:
Day-1:

Glimpses Day 1 Glimpses Day 1 Glimpses Day 1 Glimpses Day 1

Glimpses:
Day-2:

Glimpses Day 2 Glimpses Day 2 Glimpses Day 2

Shivaram Venkatesh Nellaiappan
Shivaram Venkatesh Nellaiappan
Sr. Marketing Engineer at SiFive

Read more Insights from the RISC-V Experts

Beyond the CPU and GPU: SiFive in Datacenter Infrastructure
最新文章
Beyond the CPU and GPU: SiFive in Datacenter Infrastructure
How embedded RISC-V processors in NICs, retimers, optics, switches, and security chips are overcoming modern scaling limits
The Next Leap in Datacenter AI: Orchestrating Custom Accelerators with SiFive Intelligent Control Units (ACUs)
最新文章
The Next Leap in Datacenter AI: Orchestrating Custom Accelerators with SiFive Intelligent Control Units (ACUs)
SiFive's Intelligence Family compute engines are the ideal Accelerator Control Unit (ACU) to work with customers' custom accelerators. These core and core complexes act as a dedicated, programmable RISC-V front-end controller to command and control.
SiFive 视角:RISC-V SPMP 规范正式批准,助力嵌入式安全飞跃发展
最新文章
SiFive 视角:RISC-V SPMP 规范正式批准,助力嵌入式安全飞跃发展
这项最新批准的 SPMP 功能专为增强运行实时操作系统(RTOS)的嵌入式系统中的内存保护而设计。SiFive 非常高兴能在这一进程中贡献力量,并将继续与整个生态系统保持合作,以完善 RISC-V 标准。我们坚信,SPMP 将在整个行业内获得快速普及。