All Aboard, Part 0: Introduction

I'm Palmer Dabbelt, a software engineer at SiFive and a maintainer of various RISC-V ports. I've been working with the RISC-V ISA for a few years, and it's finally starting to get ready for prime-time. We're not yet upstream in Linux or glibc, but hopefully by the end of the year we'll have the core set of system software in the relevant upstream repositories -- at which point distributions can begin porting to RISC-V and users can begin using our software. I started working with RISC-V before the user ISA had been finalized (at least v2 of the user ISA, the real one :)) and it's almost a bit scary how real things have gotten over the last few years.

While I think the core of the RISC-V software ecosystem is in decent shape, I have noticed that it's very difficult for users to get up to speed with RISC-V software due to a lack of non-code content. While SiFive has dramatically improved the documentation and user experience, there doesn't appear to be good concrete, long-form technical content about the RISC-V software ecosystem that's easy to find on a search engine. As a result, it's very hard for people who are new to RISC-V to find solutions for their problems. The mailing list has been picking up this slack for the last year or so, but as the community continues expanding, the burden of relying on users to ask questions is becoming too high.

I'll be posting a blog entry every Monday for the foreseeable future. The articles will be aimed at both users and prospective developers of the various RISC-V ports that I help maintain. I'll draft these posts so that they are interesting to read out-right, a good reference for new members of the community, and to be easy to search for on Google.

I'll see you all next Monday at our first stop: the -march, -mabi, and -mtune argument to RISC-V compilers!

Read more of the All Aboard blog series:

• All Aboard, Part 0: Introduction (current page)
• All Aboard, Part 1: The -march, -mabi, and -mtune arguments to RISC-V Compilers
• All Aboard, Part 2: Relocations in ELF Toolchains
• All Aboard, Part 3: Linker Relaxation in the RISC-V Toolchain
• All Aboard, Part 4: The RISC-V Code Models - 2026 Edition
• All Aboard, Part 5: Per-march and per-mabi Library Paths on RISC-V Systems
• All Aboard, Part 6: Booting a RISC-V Linux Kernel
• All Aboard, Part 7: Entering and Exiting the Linux Kernel on RISC-V
• All Aboard, Part 8: The RISC-V Linux Port is Upstream!
• All Aboard, Part 9: Paging and the MMU in the RISC-V Linux Kernel
• All Aboard, Part 10: How to Contribute to the RISC-V Software Ecosystem
• All Aboard, Part 11: RISC-V Hackathon, Presented by SiFive