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Article highlights rapid adoption and recent improvements made to SiFive Intelligence X280 processor.

SiFive Enhances Popular Intelligence X280 Processor

SiFive has released the latest version of its SiFive Intelligence X280 processor, which introduces new features including scalability up to a 16-core cache-coherent complex, WorldGuard trusted protection, and an interface allowing for integration between the X280 vector unit and customer-designed external AI accelerators or other coprocessors, called VCIX (Vector Coprocessor Interface eXtension).

SiFive Intelligence Processor Gets Smarter

Over the past few years, supply chain issues have shaken up the chip industry and have reinforced how important it is to have a competitive market for IP and silicon that isn’t controlled by any one company or country. That’s why we’re seeing a strong push from many regions to boost their domestic semiconductor industries, from the European Chips Act to the America Competes Act to India’s Atmanirbhar Bharat campaign. The open RISC-V architecture is playing a central role in these strategies by giving everyone an opportunity to innovate and compete.

The New Era of Design Freedom Enabled by RISC-V

SiFive and BrainChip have partnered to show their IP is compatible in SoC designs for embedded artificial intelligence (AI). The companies have demonstrated BrainChip’s neuromorphic processing unit (NPU) IP working alongside SiFive’s RISC–V host processor IP.

SiFive and BrainChip Partner to Demo IP Compatibility

AI processor maker BrainChip, which makes ultra-low-power neuromorphic chips and supporting software, and SiFive, founder of the RISC-V computing genre, today announced they have combined their respective technologies to offer chip designers optimized artificial intelligence (AI) and machine learning (ML) for edge computing.

BrainChip, SiFive Partner to Bring AI and ML to Edge Computing

SiFive has raised $175 million in a series F funding round aimed at accelerating its processor roadmap and strengthen its position in the market against Arm. The investment puts the company valuation at over $2.5 billion, and in a position to prepare itself for an initial public offering (IPO) next year.

SiFive Raises $175M To Quicken ‘Arm Intercept’ Strategy

SiFive is pulling in nearly $400m in funding this year between a new investment round and the proceeds of a business sale with the ambitious mission of eclipsing rival Arm – and the x86 world of Intel and AMD – with processor designs for everything from smartphones to servers.

SiFive bags $175m to further challenge Arm with RISC-V

Semiconductor startup SiFive said Wednesday that it has raised $175 million in a Series F funding round at a $2.5 billion post-money valuation. SiFive is the biggest startup centered around RISC-V, an open-source semiconductor technology that competes with Arm Ltd in supplying an underlying framework of chips called an instruction set architecture.

SiFive raises $175 million at $2.5 billion valuation

SiFive, Inc., today announced it has raised $175 million in a Series F financing round, valuing the RISC-V company at over $2.5 billion. The Series F round was led by Coatue Management. SiFive intends to use the funds to accelerate the development of the company’s RISC-V products, future roadmap, and develop the ecosystem for the open-source Arm challenger. Intel Capital, Sutter Hill, SK Hynix Inc., and Qualcomm Ventures are also investors. The company has now raised over $350M in capital.

SiFive Inc., a computer chip startup that’s developing processor technology based on the open-source RISC-V instruction set architecture, said today it has raised a hefty $175 million in a late-stage round of funding.

Arm rival SiFive raises $175M to accelerate development of its alternative RISC-V chip architecture

Chip design firm SiFive has raised $175 million at a $2.5 billion as RISC-V emerges as an alternative processor architecture.

The funding comes at a time when RISC-V is showing greater momentum as an alternative processor architecture to those run by Intel/AMD and Arm.

RISC-V chip designer SiFive raises $175M at a $2.5 billion valuation

Nvidia's attempt to buy Arm scared many in the chip industry. That's been a boon to SiFive...

SiFive just raised $175M in new funding. Its CEO says the failed Nvidia-Arm deal boosted its business

Chip startup SiFive Inc. raised $175 million from investors such as Intel Corp. and Qualcomm Inc., giving it enough funding to work toward going public.

Chip Designer SiFive Raises $175 Million, Setting Stage for IPO

SiFive, Inc., a RISC-V chip technology startup in Silicon Valley, said on Wednesday it raised $175 million in its latest round of funding and is now valued at $2.5 billion.

RISC-V chip technology firm SiFive raises $175 mln, valued at $2.5 bln

The new funding, which values SiFive at $2.5 billion, was designed to help the company establish RISC-V as a real option in the market for third-party chip designs dominated by Arm.

SiFive raises $175 million in bid to unseat Arm with RISC-V

This group of semiconductor giants and chip startups are poised to make big waves in 2022 between new products, merger and acquisition deals and other newsworthy events. As Arm’s future stewardship has become increasingly uncertain, SiFive has risen as an alternative chip designer for companies that want to make their own processors. The main differentiator for SiFive: its use of the free and open RISC-V instruction set architecture.

The 10 Hottest Semiconductor Companies To Watch In 2022

Chip technology firm SiFive Inc on Thursday said it has sped up its computing core designs by 40% and now has a headcount of 700 employees, with plans to double its staff by next year.

SiFive speeds up computing chip designs as it staffs up

A startup called SiFive announced a new processor design Thursday that could revamp mobile phones, cars and other digital devices if the company's plans work out. Its Performance P650 design comes with a 50% speed boost over the P550 that arrived in June. 

SiFive's new chip could lead to revamped phone brains in 2023

The design for the P650 processor, which other companies will take and turn into working products, is the highest-performing member of the SiFive Performance family, which the company said is expected to be the fastest licensable RISC-V processor IP core. It’s another step in the ongoing quest to show that the open source hardware movement can keep pace with rivals such as Arm and Intel.

SiFive moves into high-end RISC-V processors with P650 design

SiFive: RISC-V has no limits. SiFive emerged from stealth mode as a developer of small, low-power cores for microcontrollers in 2016. By late 2020, the company had a chip that could run Linux and this week said that it developed a CPU core that is comparable to modern offerings designed by Intel and Arm. The company believes that such high-performance designs could be used for a wide variety of applications, including server-grade system-on-chips with 128-cores.

SiFive Envisions 128-Core RISC-V SoCs as Gap With x86 and Arm Closes

The performance of the as yet nameless RISC-V core should be 50 percent higher than that of its predecessor, and there is also the option for 16-core clusters. [GER]

SiFive reckons its fastest RISC-V processor core yet is closing the gap on being a mainstream computing alternative to x86 and Arm.

We're closing the gap with Arm and x86, claims SiFive: New RISC-V CPU core for PCs, servers, mobile incoming

When you need to do audio, voice or image processing at the network edge or on a battery budget. 

Proposed RISC-V vector instructions crank up computing power on small devices

With the HiFive Unmatched, there is finally a powerful developer board with RISC-V, the software is also well-engineered. Apple, Google, Nvidia, Samsung, Qualcomm - they all use them: The open instruction set architecture RISC-V is primarily used in embedded controllers in smartphones, for example. With the HiFive Unmatched, however, Sifive has released a well-equipped mini-ITX board that is aimed at developers or people who want to try out RISC-V. [GER]

A few weeks ago I finally received the HiFive Unmatched from SiFive as their flagship RISC-V development board. As a reminder this is their mini-ITX development board that is powered by their U740 SoC and features 16GB of DDR4 system memory, one PCI Express x16 slot that can work with AMD Radeon graphics cards on Linux, and other features. It's been a delight playing with this developer platform and enclosed are some early benchmarks as well showing off the U740 performance as well as how the Linux software support/performance has been evolving.

SiFive HiFive Unmatched Hands-On, Initial RISC-V Performance Benchmarks

The company is pushing the capabilities of the heretofore predominately embedded and IoT-focused RISC-V ISA further into visibility with the introduction of the SiFive Performance and SiFive Intelligence processor lines. The latter integrates RISC-V vector extensions and SiFive's proprietary vector extensions for use with AI/ML applications.

SiFive shepherds RISC-V ISA to enterprise applications, broader adoption

With Canonical announcing Ubuntu support for so much new hardware, the announcement of Ubuntu ported to a new architecture can go unnoticed. But today, we have a big one. Working  with the leading RISC-V core IP designer and development board manufacturer, SiFive, we are proud to announce the first Ubuntu release for two of the most prominent SiFive boards, Unmatched and Unleashed.

Canonical enables Ubuntu on SiFive’s HiFive RISC-V boards

Today’s announcement from SiFive comes in two parts; this part is significant as it recognizes that Intel will be enabling SiFive’s IP portfolio on its 7nm manufacturing process for upcoming foundry customers. 

[Note - this process technology is now known as 'Intel 4']

Intel Licenses SiFive’s Portfolio for Intel Foundry Services on 7nm

Intel said it is working with SiFive to ensure that the new cores can be manufactured in its newest 7-nanometer chip factories. Intel will offer those manufacturing services to outside chip companies as part of its effort to become a chip contract manufacturer.

SiFive Inc on Tuesday released a new computing chip design that aims to challenge Arm Ltd's dominance in smartphone chips

Startup SiFive announced a faster new processor design, the P550, that means its chips can better challenge Arm, the leader in processors for mobile devices and many other electronics products. And the company also deepened a partnership with another rival, Intel, for actually manufacturing the chips.

SiFive chip design challenges Arm and leads to Intel alliance

The Barcelona Supercomputing Center (BSC) has been collaborating with Codeplay Software and SiFive to implement support for the RISC-V V-extension v0.10 in the LLVM compilation infrastructure. Thanks to this support, users of RISC-V will be able to take advantage of vector computation capabilities of the RISC-V V-extension through C/C++ intrinsics.

BSC, Codeplay, and SiFive help accelerate applications on RISC-V thanks to V-extension support in LLVM

The very fact that Tenstorrent chose to use SiFive-developed RISC-V CPU design is noteworthy by itself and is a testament to the new architecture.

Jim Keller-Led Tenstorrent Licenses RISC-V for AI

“RISC-V is an important element in providing additional capabilities and options for new and existing customers,” said Takeshi Kataoka, Senior Vice President, General Manager of Automotive Solution Business Unit at Renesas. “We are very excited to work with SiFive as their lead partner to develop next-generation semiconductor solutions through the collaboration of our accumulated expertise in the automotive field, and SiFive’s high-end RISC-V technologies.”

Renesas and SiFive Partner to Jointly-Develop Next-Generation High-End RISC-V Solutions for Automotive Applications 

SiFive on Tuesday said that its OpenFive division has successfully taped out the company's first system-on-chip (SoC) on TSMC's N5 process technology. The SoC can be used for AI and HPC applications and can be further customized by SiFive customers to meet their needs.

SiFive Tapes Out First 5nm TSMC RISC-V Chip With 7.2 Gbps HBM3

In the event that Nvidia compromises most processor-related ARM IPs, SiFive's RISC-V scalable CPUs could see increased adoption even from mobile and smartphone OEMs. SiFive is already prepared to meet the increased demand with its updated AI-focused RISC-V microarchitecture that enables different classes of performance, efficiency and features for server-grade, HPC and even desktop PC systems.

SiFive announces new RISC-V processor architecture plus its first-ever desktop PC processor

One of the largest SoC developers is now relying on RISC-V: Qualcomm integrates cores with the open instruction set architecture for embedded use in current and future Snapdragon chips.

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At the annual RISC-V Summit this week, Samsung disclosed the use SiFive’s RISC-V cores for upcoming chips for a variety of applications. The company is joining a growing list of leading high-tech companies that have adopted the RISC-V architecture

Samsung to use SiFive RISC-V Cores for SoCs, Automotive, 5G Applications

This week saw another indication that open source hardware is ready to seriously vie for a slice of the enterprise IT pie. On Monday the major company behind the open source RISC-V processor, SiFive, reported it had raised $50.6 million in a Series C funding round, bringing total funding to $64.1 million.

RISC-V Silicon Startup Raises $50.6 Million and Inks Western Digital Deal

SiFive has raised $50.6 million in a third round of funding to further its ambition to create a new licensing model for the semiconductor industry. San Francisco-based SiFive wants to democratize access to custom silicon chip designs. The company’s founders invented RISC-V, a free and open instruction set architecture for modern microprocessors. SiFive is taking that architecture and making it easy to design the custom variants that companies need.

SiFive raises $50.6 million for licensable custom microprocessors

By now, you’ve likely heard someone tell you: Moore’s Law is dead. To be sure, it is worthwhile to point out that the design aspect of Moore’s Law is – in most circumstances – very much alive. There are still techniques to be discovered to make the transistors smaller, for them to work faster, and to still put more of them in the same footprint. Rather, it is the economics behind Moore’s Law that has clearly reached its endpoint. Chips might continue to get smaller and faster. But if the economics mean that almost no one can afford to buy them, where exactly are we headed?

Moore’s Law is Dead: So, Let’s Talk About the Future of SoCs

Only months after debuting the Freedom U540, the world's first Linux-compatible processor based on the open-source RISC-V chip architecture, RISC-V chipmaker SiFive has surprised the open-source community again by unveiling a full development board built around the ISA.

First Open-Source RISC-V SoC for Linux Released

While software is eating the world, open source hardware might soon be eating the data center. Definitely not tomorrow or next month, and probably not even next year, but sooner than you think, there might be as much open source hardware as the old-fashioned proprietary kind running data centers.  Need proof? Take a look at RISC-V, an open processor architecture.

Is Open Source RISC-V Ready to Take on Intel, AMD, and ARM in the Data Center?

For low-power and embedded purposes RISC-V, an ISA developed principally by researchers at UC Berkeley with significant outside contributions, is gaining popularity.  While early RISC-V devices have been intended for embedded applications and IoT devices, SiFive has released the first RISC-V SoC (Freedom U540) and SBC (Hi-Five Unleashed) which are powerful enough to run Linux distributions.

HiFive Unleashed: The first Linux-capable RISC-V single board computer is here

Palmer Dabbelt will give a talk about Igniting the Open Hardware Ecosystem with RISC-V. SiFive's Freedom U500 is the World's First Linux-capable Open Source SoC Platform at FOSDEM 2018.

Interview with Palmer Dabbelt: Igniting the Open Hardware Ecosystem with RISC-V. SiFive's Freedom U500 is the World's First Linux-capable Open Source SoC Platform

“Our vision is to enable two guys in a garage to build a custom chip.” Thus spake Jack Kang, Vice President of SiFive, the 40-person startup making RISC-V chips. SiFive isn’t just another company pulling the RISC-V bandwagon. They’re trying to change the way we create SoCs. The au courant open-source processor design is just a means to that end.

Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced SiFive, the first fabless provider of customized, open-source-enabled semiconductors, has joined Microsemi's new Mi-V™ RISC-V ecosystem, further building out the growing ecosystem and expanding the number of RISC-V designs users can consider. Microsemi will leverage its strategic relationship with SiFive and other ecosystem participants to increase adoption of RISC-V open instruction set architecture (ISA) central processing units (CPUs) and maximize their leadership positions with this expanding design technology.

SiFive Joins Microsemi's New Mi-V Ecosystem to Accelerate Adoption of RISC-V Open Instruction Set Architecture

Western Digital is known for its storage products. What many do not realize is that the company ships over 1 billion processor cores within its products each year and is moving toward 2 billion per year. At the workshop, Western Digital CTO Martin Fink announced that over the next few years those billion plus processors will be transitioned over to RISC-V.

Western Digital Gives A Billion Unit Boost To Open Source RISC-V CPU

One of the barriers to silicon success has always been design costs, especially if you are an emerging company or targeting an emerging market such as IoT. Today design start costs are dominated by IP which is paid at the start of the project and that is after costly IP evaluations and other IP verification and integration challenges. Given that, reducing design costs and enabling design starts has always been a major industry focus starting with the fabless semiconductor transformation that began 30 years ago, which brings us to the DesignShare announcement made by SiFive and Flex Logix last week.

DesignShare is all About Enabling Design Wins!

SiFive and FlexLogix have teamed up to offer embedded FPGAs in the DesignShare development program. This is the third IP vendor that SemiAccurate knows of to join that program and it is an interesting idea.  SiFive’s DesignShare program is unique in it’s aim to lower the barriers of entry for companies interested in making silicon.

FlexLogix joins SiFive’s DesignShare program

RISC-V is a free and open instruction set architecture [ISA] designed to enable chips across the full spectrum of computing devices, from embedded devices to the data centre,” said the firm. “The release of the U54-MC Coreplex marks the architecture’s expansion into the application processor space – opening entirely new use cases for RISC-V. It is ideal for applications which need full operating system support such as AI, machine learning, networking, gateways and smart IoT devices.

The Coreplex U54-MC contains four U54 CPUs and a single E51 CPU and is the first Coreplex processor core to offer multicore support and support for cache coherence. The U54 cores support the RV64GC ISA with a five-stage, in-order pipeline ALU. The 64bit E51 CPU serves as a management core and is fully coherent with the U54 cores. The U54-MC Coreplex is ideal for applications which need full operating system support such as AI, machine learning, networking, gateways, and smart IoT devices.

SiFive launches Linux-ready RISC-V quad-core processor

Linux fanboys tend to announce a lot of “year of” events. There is the year of the desktop which appears to be every year and still never happens and now there is the year of RISC V Linux processor. SiFive has declared that 2018 will be the year of RISC V Linux processor, so mark your penguin diaries accordingly.  In the UK there will be all sorts of events planned, including guess the weight of Linus Torvalds competitions, there will be penguin tossing at Slough.

2018 will be the year of the RISC V Linux processors

Last year, Silicon Valley Startup SiFive released the first open source SoC (system on a chip), which was named Freeform Everywhere 310. Now, going one step ahead from the embedded systems, the company has released U54-MC Coreplex IP, which is the world’s first RISC-V based 64-bit quad-core CPU that supports fully featured operating systems like Linux.

Linux Gets Its First Multi-Core, RISC-V Based Open Source Processor

When it released its first open-source system on a chip, the Freeform Everywhere 310, last year, Silicon Valley startup SiFive was aiming to push the RISC-V ("risk five") architecture to transform the hardware industry in the way that Linux transformed the software industry. Now the company has delivered further on that promise with the release of the U54-MC Coreplex , the first RISC-V-based chip that supports Linux, Unix, and FreeBSD.

Linux Now Has its First Open Source RISC-V Processor

SiFive launched U54-MC Coreplex IP, a RISC-V based, 64-bit, quadcore real-time capable application processor with support for full featured operating systems such as Linux. The cores utilize a five-stage in-order pipeline, support the RV64GC ISA and cache coherence. It is targeted at AI, machine learning, networking, gateways and smart IoT devices.

At the Linley Processor Conference today, SiFive, the semiconductor company building chips around the Open RISC-V instruction set has announced the availability of a quadcore processor that runs Linux. We’ve seen RISC-V implementations before, and SiFive has already released silicon-based on the RISC-V ISA. These implementations are rather small, though, and this is the first implementation designed for more than simple embedded devices.

SiFive has taped out and started licensing its U54-MC Coreplex, its first RISC-V IP designed to run Linux. The design lags the performance of a comparable ARM Cortex-A53 but shows progress creating a commercial market for the open-source instruction set architecture.

The RISC-V universe just got a little bigger with SiFive’s 1.5 GHz U54-MC Coreplex (Fig. 1). The four U54 cores implement RV64GC that includes support for hardware multiple and divide, atomic instructions, 16-bit compressed instructions, and single and double precision floating point support.

SiFive has taped out the first multi-core RISC-V based processor design, and the first to run Linux, featuring 4x 1.5GHz "U54" cores and a management core. SiFive announced "early access" availability of the 64-bit, quad-core U54-MC Coreplex – the first Linux-ready application processor built around the open source RISC-V architecture.

SiFive Unleashes the First Linux-Ready, 64-Bit RISC-V SoC

It is out of this that SiFive began.  SiFive was founded by the creators of the first commercially successful open RISC architecture, known as RISC-V.  RISC-V was developed at Berkeley, fittingly, in 2010 and was designed to be a truly useful, general purpose RISC processor, easy to design with, easy to code for, and with enough features to be commercially useful, not limited to the classroom.  It is called the RISC-V because it is the fifth RISC design developed at Berkeley, RISC I and RISC II being designed in 1981, followed by SOAR (Smalltalk On A RISC) in 1984 and SPUR (Symbolic Processing Using RISC) in 1988.  RISC-V has already proved to be a success, it is licensed freely, and in a way (BSD license) that allows products that use it to be either open, or proprietary.  One of the more well known users is Nvidia, which announced they are replacing their own proprietary FALCON processors (used in their GPUs and Tegra processors) with RISC-V.  Samsung, Qualcomm, and others are already using RISC-V.  These cores are often so deeply embedded that their existence goes without mention, but they are there, working in the background to make whatever tech needs to work, work.

开源是当今最热门的话题之一，也是未来的趋势，就像1998年时任微软CEO的鲍尔默痛斥Linux是癌症，而如今的CEO 却称“Microsoft love Linux”，因为开源“以人为本”，然而开源的商业化是一条必行却又难行的路。

如今的处理器、SoC基本被x86与ARM 这样封闭的指令集架构（ISA）所统治。所以谁能成为微处理器中的 Linux ，成为业界探讨与期待的事情。而目前RISC-V成为最受关注的对象。

5月8日，第六届RISC-V技术研讨会在上海交通大学举行，这是RISC-V在华首度亮相。参会的国内外顶尖学者和企业人员超过200名，RISC-V发明者创建的SiFive公司分享了RISC-V指令集和其相关前景应用。

SiFive让RISC-V商业化之路不再难行

由免费开源RISC-V指令集架构发明者创建的企业SiFive于今日在上海参加RISC-V基金会主办，NVIDIA和上海交通大学联合承办的第六届RISC-V技术研讨会，首次在中国与到会的200余名国内外顶尖学者和企业共同分享RISC-V指令集和其相关前景应用。作为首家基于免费开源RISC-V指令集架构的定制半导体公司，SiFive还在研讨会上分享了公司的最新进展 – SiFive即将推出目前访问RISC-V内核最快捷也最简单的方式 – Coreplex IP产品。随着RISC-V生态系统的快速发展，SiFive Coreplex IP设计已成为RISC-V内核的实际领导者，拥有比任何其他RISC-V架构厂商更多的客户群、硅产品和开发板。另外，SiFive还提供了简易的“调研-评估-购买”(Study – Evaluate – Buy)的采购流程，帮助工程师们迅速获得实用的Coreplex IP RTL源代码。

SiFive携全新产品和商业模式让RISC-V触手可及

在你购买一个PC或者服务器的时候，在做主芯片选择的时候，你会想到X86架构，或者至少时候ARM架构的芯片。

但是像软件里的LINUX一样，一个开源的架构项目准备打破这个由Intel、AMD和ARM主导的芯片市场，那就是Risc-V。

这个由加州大学伯克利分校研究院在2010年打造的芯片架构是免费向所有人开放的。而据介绍，开发者可以基于这个架构开发应用于PC、服务器、智能手机、可穿戴和其他设备的芯片。

初创企业SiFive是首个基于Risc-V架构开拓业务的公司，这个公司也是首个将Risc-V指令转为硅片的企业。日前，该公司宣布，他们已经开发出了两款芯片设计，并能够将其授权给客户。

SiFive让RISC-V商业化之路不再难行 

Last year, SiFive went fishing for engineers willing to test out chips based on the RISC-V instruction set, releasing a basic core called Rocket that anyone could download and modify. But now the company, whose founders invented RISC-V, is using richer bait for more ambitious customers.

Last week, SiFive started selling two embedded cores under the brand Coreplex, with applications ranging from wearables to servers. The company is aiming to lower the bar for engineers trained on Intel or ARM instruction sets to take RISC-V for a spin, when few companies appear to be turned off by the inflexibility or licensing fees of rival technology.

A Patient Disciple of RISC-V, SiFive Starts Selling Cores

SiFive is pioneering a new model in the semiconductor business and to do so has raised $8.5 million in a second round of funding, led by Spark Capital.

San Francisco-based SiFive is on a mission to democratize access to custom silicon chip designs. The company’s founders invented RISC-V, a free and open instruction set architecture for modern microprocessors. It consists of all of the software instructions needed to program a microprocessor based on the RISC-V architecture. And SiFive is taking that architecture and making it easy to design the custom variants that companies need.

SiFive raises $8.5 million for licensable custom microprocessors

This week, SiFive announced a new “study-evaluate-buy” purchase process, that lets developers “get their hands on Coreplex IP RTL in a matter of minutes.” The immediately downloadable E31 Coreplex and E51 Coreplex IP RTL is described as “fully synthesizable and verified soft IP implementations that scale across multiple design nodes, making them ideal for your next SoC design.” On its Coreplex IP evaluation web page, SiFive describes the IP evaluation and purchase as being fast, NDA-free, and with a pricing model that is not based on royalties.

Design your own RISC-V SoC with SiFive’s new “hassle-free” process

SiFive Inc. wants to give businesses access to custom-designed silicon chips at an affordable price, and today the San Francisco-based semiconductor startup announced that ii has closed an $8.5 million Series B funding round.

The round was led by Spark Capital, and it also included participation from Osage University Partners and existing investor Sutter Hill Ventures. SiFive’s Series B round brings the startup’s total investments to date to $13.5 million.

SiFive raises $8.5M to build low-cost custom chips

A startup called SiFive is the first to make a business out of the RISC-V architecture. The company is also the first to convert the RISC-V instruction set architecture into actual silicon. The company on Thursday announced it has created two new chip designs that can be licensed.

Open-source chip mimics Linux's path to take on closed x86, ARM CPUs

There has been an upswell of interest in custom, open hardware among makers, in which community-developed and shared designs abound. The availability of low-cost development boards such as Arduino and Raspberry Pi, together with open source software, has made it easier to get started with making innovative, new hardware designs.

SiFive Is Bringing Open Source to the Chip Level

Come hang out for 30 or so minutes and talk to Jack Kang, VP of Product and Business Development at SiFive. Join this chat to learn about RISC-V, the free and open Instruction Set. Ask questions about what it means to have open-source chips, and how SiFive plans to help everybody—from the smallest company, inventor, and maker, get access to custom silicon.

Open Source Chip Design Hack Chat Transcript

SiFive is the first fabless provider of customized, open-source-enabled semiconductors. The RISC-V ISA has been central to our vision of enabling a whole new range of applications for everyone. In November 2016, we announced the availability of the Freedom Everywhere 310 (FE310) SoC, the industry's first commercially available chip based on RISC-V. Bringing the first commercially available SoC based on the RISC-V ISA is a huge milestone for the open-source hardware community.

Customer Corner: SiFive's Freedom Everywhere 310 (FE310) SoC Alternative

The SiFive business model is that lots of people are locked out of silicon. SiFive can do custom design and deliver chips. "We believe we can do it cheaper, quicker and more predictably than anyone else.” They have also been getting lots of calls to help with designs. Growing the RISC-V ecosystem is a big opportunity.

The traditional semiconductor business models take a lot of resources, so you have to pick the winners. But there aren't any $1B sockets anymore, so you can't easily pick the winners. The market is fragmented. SiFive wants to give everyone a chance. In a bit more detail, they will do a customer microcontroller platform and deliver 100 or so chips for under $100K.

RISC-V "The thing that you learn and the thing that you use are the same"

源自柏克萊大學的開放原始碼指令集架構(ISA)處理器RISC-V，目前已陸續獲得多家科技大廠支持，開始應用在自家產品中。為進一步推動RISC-V處理器的商業應用，由柏克萊教授與研究生共同創辦了一家名為SiFive的新創晶片設計服務公司，並獲得台積電大力奧援。目前SiFive已推出基於台積電0.18微米與28奈米製程的微控制器(MCU)與微處理器SoC平台。

專訪SiFive產品暨業務開發總監剛至堅　開源處理器生態系統邁開大步

In an interview, Jack Kang, VP of Product and Business Development at SiFive, discusses the FE310 chip, which will allow IoT vendors to build their own custom SoC on top of it

SiFive is a relatively new fabless chip manufacturing startup that is developing fully open source chips. Its new FE310 chip is its first chip (and apparently the first open source chip) targeted at IoT devices.

SiFive rolls out fully open source chip for IoT devices

2016 was a great year for Open Hardware. The Open Source Hardware Association released their certification program, and late in the year, a few silicon wizards met in Mountain View to show off the latest happenings in the RISC-V instruction set architecture.

We’ve seen a lot of RISC-V stuff in recent months, from OnChip’s Open-V, and now the HiFive 1 from SiFive. The folks at SiFive offered to give me a look at the HiFive 1, so here it is, the first hands-on with the first Open Hardware microcontroller.

Hands On With The First Open Source Microcontroller

One of the lessons learned years ago in the open-source Linux world is that free software isn’t always good enough. Consequently, being able to add commercial value around freeware can turn into a lucrative business.

Enter SiFive, a startup that has been building customized platforms based on the RISC-V CPU. Started by the creators of the RISC V instruction set architecture (ISA), the company’s stated goal is to shake up the economics of the chip industry.

Moore's Law is dead...just not in the way everyone thinks. Technological advances keep allowing chips to scale, but the economics are another story – particularly for smaller companies that can't afford chips in the volumes that the big chipmakers would like from their customers.

The solution, according to San Francisco-based startup, SiFive, is open-source hardware, specifically an architecture developed by the company's founders called RISC-V (pronounced “risk-five”). Done right SiFive, which was awarded Startup of the Year at the 2016 Creativity in Electronics (ACE) Awards, believes that RISC-V will do for the hardware industry what Linux has done for software.

SiFive Is Setting Silicon Free with Open-Source Chips

The best and brightest were on display last night as UBM announced the 2016 Annual Creativity in Electronics (ACE) Awards winners during a ceremony held in conjunction with ESC Silicon Valley and BIOMEDevice San Jose. The awards, presented in partnership with EETimes and EDN, showcase the best in today’s electronics industry, including the hottest new products, start-ups, design teams, executives, and more.

The RISC-V footprint is expanding with the commercial availability of open-source chips and related development boards from silicon startups like SiFive and OnChip.

The open-source hardware movement's journey from academia to the commercial realm is finally gaining some momentum. This is in large part thanks to free RISC-V instruction set architecture (ISA), which was developed at the University of California, Berkeley a few years ago.

Open Source RISC-V Architecture Makes Strides Towards Customizable SoCs

One of the announcements at the recent RISC-V workshop was by SiFive. This is the company started by the creators of the RISC-V instruction set architecture (Krste, Andrew, and Yunsup) to commercialize silicon implementations.

Four months ago, at the previous RISC-V workshop, they announced FPGA implementations of the two flavors, Freedom Everywhere (16-bit microcontroller) and Freedom Unleashed (64-bit multi-core, high performance). They also announced that silicon would be coming "soon."

In a nutshell, RISC-V is an instruction set architecture (ISA) that scales from 16-bit to 128-bit register platforms. The E310 is targets the Cortex-M0 space, but it can run at 320 MHz while sipping power—making it an interesting solution for the Internet of Things (IoT). The chip is available on the HiFive1 board ... that has an Arduino form factor.

Will RISC-V Rescue the Internet of Things?

Startup SiFive started selling today a $59 Arduino board running its first RISC-V-based SoC and made open source RTL code available online for the chip. The news marks a milestone for a still nascent open source hardware movement.

Open source cores have been available previously but they tended to be academic efforts or lacked broad commercial support. The HiFive board is intended to drive demand for custom SoCs SiFive will design and comes with a growing pool of open source Linux variants and tools fed by an expanding foundation that maintains the RISC-V instruction set.

The RISC-V ISA has seen an uptick in popularity as of late — almost as if there’s a conference going on right now — thanks to the fact that this instruction set is big-O Open. This openness allows anyone to build their own software and hardware. Of course, getting your hands on a RISC-V chip has until now, been a bit difficult. You could always go over to opencores, grab some VHDL, and run a RISC-V chip on an FPGA. Last week, OnChip released the RISC-V Open-V in real, tangible silicon.

HiFive1: RISC-V In An Arduino Form Factor

SiFive wants to democratize the custom chip business, and so today it is launching the industry’s first open-source RISC-V system-on-chip processor. The Freedom Everywhere 310 SoC and HiFive1 development board will enable a wide variety of system architects, embedded designers, and Internet of  Things providers — people who normally have to rely on chip engineers for the detailed engineering work — to create their own products.

SiFive Launches Open Source RISC-V Custom Chip

Microsemi's new RV32IM RISC-V core, developed in collaboration with SiFive, enables customers to design with an open instruction set architecture (ISA), enabling complete portability and a more secure processor architecture governed by a permissive BSD license. RISC-V is a new ISA which is now a standard open architecture under the governance of the RISC-V Foundation. RISC-V offers a compelling soft processor solution for Microsemi's low power, reliable, secure FPGAs.

Microsemi is First FPGA Provider to Offer Open Architecture RISC&#8209;V IP Core and Comprehensive Software Solution for Embedded Designs

Since its formation just last year, SiFive has been riding the RISC-V rocket from purely academic interest to first commercialization. In an exclusive discussion, I talked with CEO Stefan Dyckerhoff and VP of Product and Business Development Jack Kang about their progress so far and what may be coming next.

SiFive execs share ideas on their RISC-V strategy

In their 2014 technical report for the University of California at Berkeley, Krste Asanovic and Professor David Patterson – who developed the concepts behind the SPARC architecture in the 1980s – argued that, while there are good commercial reasons for processor makers to maintain proprietary instruction sets, there is no good technical reason for users to adopt them. Their proposal was for an instruction set architecture (ISA) offered on a similar basis to open source software that could stimulate an ecosystem similar to that built around Linux.

As their proposal represented the fifth generation of RISC processor design, it was called RISC-V.

As many would-be open hardware manufacturers have discovered, free-licensed computer chips are nearly non-existent. However, SiFive, a recently announced startup in San Francisco, is hoping to change that with its custom chip designs. SiFive has its origins in the RISC-V instruction set architecture (ISA) developed in the Computer Science Division of the Electrical Engineering and Computer Science Department at the University of California, Berkeley.

Creating the free-licensed semiconductor market

It has been a year since EE Times produced a version16.1 of the Silicon 60. Over that time while the global economic situation can — at best — be said to have stabilized the semiconductor and electronics industries are on the edge of "great expectations.” There seems no doubt that the Internet of Things will have a revolutionary impact on how people can live their lives, but exactly how that will manifest itself in terms of components, software, platforms, legal and business models, is not yet clear nor is the next big thing.

EE Times Silicon 60: 2016’s Emerging Companies to Watch

RISC-V (pronounced “risk five”) is an open, 32/64-bit RISC microprocessor architecture first developed at the Computer Science Division of the EECS Department at the U. of California, Berkeley. Now it’s managed by the RISC-V Foundation. If you are an aficionado of processor architectures and you’re looking to get your feet wet with the RISC-V architecture, SiFive has released three Freedom FPGA Platforms based on Xilinx All Programmable devices that allow you to start working with the RISC-V ISA immediately.

Itching to Play With the Open-Source RISC-V Processor? Here Are Three Xilinx-Based Kits to Start With

A couple of weeks ago I talked to Krste Asanović and Jack Kang of SiFive. One of their motivations is to bring the cost reduction that goes along with open-source software (and instruction sets!) to the hardware world. There is an increasing move in this direction as companies like Facebook, IBM, and Google put parts of their server infrastructure into the public domain. This is especially important in semiconductors since Moore's law has run into a wall, at least economically, even though we have a couple more process generations coming at us.

SiFive: A RISC-V Fabless Semiconductor Company

A week or so ago I talked to Krste Asanović, who is the UC Berkeley professor who led the project to define RISC-V, chairman of the RISC-V foundation, and in July co-founded a fabless semiconductor company, SiFive, to produce silicon implementations (and IP). I'll talk about SiFive in Breakfast Bytes one day next week. RISC-V has taken off strongly in academic circles due to its unrestricted availability compared to other instruction sets, which are often not really ideal for academic work, and/or come with legal encumbrance.

SiFive recently unveiled its flagship Freedom family of SoC platforms. Built around the RISC-V ISA invented by the company’s founders at the University of California, Berkeley, the Freedom U500 and Freedom E300 platforms represent a new approach to designing and producing SoCs that redefines traditional silicon business models and reverses prohibitively rising licensing, design and implementation costs.

SiFive – Freedom Family of RISC-V ISA-Based SoC Platforms

Makers are the epitome of what big chip vendors used to consider a waste of time for their valuable salesfolk. “Fred in the shed,” as they said. No volume, no ROI. “Stick with Tier 1s.”

SiFive is a San Francisco-based fabless chip manufacturing startup that is developing the first fully open source chips. The company, which launched earlier this month, announced two chips of their flagship platform:  Freedom U500 and Freedom E300, each targeting different audience.

Why the Time Is Right for Open Source to Meet Hardware

SiFive, a startup from San Francisco, is trying to democratize the access to the world of SoC designing and manufacturing by giving the ability of customizing silicon to the smallest company, inventor, or maker, and taking “the hard parts of building chips working with 3rd part IP, EDA tools and foundries. SiFive is a fabless semiconductor company building customizable SoCs. SiFive takes benefits from using RISC-V in their SoC design. Some of inventors of the open source ISA RISC-V are behind SiFive.

An Open-Source SoCs with RISC-V From SiFive

As many of you may already know, SiFive is the first company that will make open source ISA Risc-V SoCs. What will be open and what not ? This was main question that people ask. In this video they answered that they will open as much as they can.PCI-E 3 controllers and some other 3-d party stuff will remain closed. They said time to develop some controllers and other 3d party tools and all to be open sourced will take ~ another 2 years of work.

SiFive has introduced the Freedom family of open-source SoC-platform intellectual property based on the RISC-V instruction set architecture. The company offers the Freedom U500 and Freedom E300 processing platforms that are a new approach to designing and producing SoCs in that they are based on open-source and extensible architecture with no licensing fees.

SiFive Introduces E300 & U500 Open-Source Chip Platforms

SiFive, a new Silicon Valley startup, is teaming up with RISC-V Foundation and the infrastructure set to develop open source chip products. Two chips are in development – Freedom Unleashed (designed for machine learning, storage and networking) and Freedom Everywhere (designed for low-power devices in the “Internet of Things” market). SiFive is trying to drive down the cost of chip manufacturing, open the industry up to designers and engineers, and squeeze into an industry that has several barriers of entry.

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SiFive 与 AMD 展开合作，优化基于 RISC-V 数据中心服务器的 AMD ROCm

SiFive 推出 BigSky 开发服务器，加速 RISC-V 挺进数据中心

SiFive 推出第三代 Performance P550 与 P570 IP，树立 RISC-V 高性能新标杆