September 13, 2018

Wasiela Brings Encryption, FEC and Connectivity IP to DesignShare

SiFive, the leading provider of commercial RISC-V processor IP, today announced that Wasiela, a provider of innovative PHY-layer IP from the system and algorithmic levels all the way to implementation, has joined the DesignShare ecosystem. The availability of Wasiela encryption, forward error correction (FEC) and connectivity IP through the program will ease the development of reliable and secure high-throughput data communications for the RISC-V platform.

Specific IP Wasiela plans to make available through DesignShare’s secure ecosystem includes its AES IP core and ECC for encryption; BCH, Reed Solomon, LDPC and Turbo Encoders/Decoders for FEC; and ZigBee Transceiver PHY and OFDM-based cores for connectivity. All Wasiela cores serve as accelerators or slave peripherals to RISC-V processors and are easily integrated via the TileLink interface.

“RISC-V represents a new wave of growth and innovation in the semiconductor industry, and we are excited to join SiFive in the DesignShare ecosystem,” said Ahmed Shalash, President, Wasiela. “Wasiela enables system designers to incorporate leading IP to ensure the quality and consistency of data communications for consumer electronics on any platform, now including RISC-V.”

Any company, inventor or maker can harness the power of custom silicon with little to no upfront risk through the SiFive DesignShare program. To lower the costs of bringing a chip from design to realization, DesignShare partners like Wasiela offer pre-integrated solutions that enable users to develop their prototypes without the investment in upfront engineering costs typically required.

“Wasiela’s IP can offer DesignShare participants an edge in developing ultra-low power, configurable designs to ensure the integrity of data communications,” said Shafy Eltoukhy, vice president of operations and head of DesignShare for SiFive. “The growing ecosystem of DesignShare IP providers like Wasiela ensures that aspiring system designers have a catalog of IP from which to choose when designing their SoC.”

Since DesignShare launched in 2017, the ecosystem has grown to include a wide range of IP solutions, from debug and trace technology to security cores and reconfigurable FPGA.

About SiFive

SiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. Led by a team of industry veterans and founded by the inventors of RISC-V, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers to build customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital, Osage University Partners, Intel Capital and Chengwei Capital, along with strategic partners Huami, SK Telecom and Western Digital. For more information, visit


Jamie Feller
SHIFT Communications for SiFive
(415) 591-8432