September 03, 2020

SiFive and Barcelona Supercomputing Center Advance Industry Adoption of RISC-V Vector Extension

The new API adds critical capabilities to widely used compilers, GCC & LLVM

SAN MATEO, Calif. Sep 3, 2020 - SiFive, Inc., the leading provider of commercial RISC-V processor IP and silicon solutions, today announced several new updates to their leading RISC-V portfolio in the areas of security, and vector processing. In collaboration with the Barcelona Supercomputing Center, SiFive created an API for vector intrinsics for popular open-source compilers GCC, and LLVM. Additionally, SiFive reports that the SiFive Shield Hardware Cryptographic Accelerator (HCA) true random number generator (TRNG) has successfully passed conformance evaluation to SP 800-90B standard, to enable FIPS 140 certified security solutions.

RISC-V Vector Processing
The new API will speed up the development of vector processor applications using RISC-V processor cores with RISC-V Vector Extension (RVV) 1.0 support, such as the upcoming SiFive Intelligence line of products. The API is available on GitHub now and will be upstreamed to GCC and LLVM compilers once the RVV specification is ratified. SiFive previously added upstream support for the RISC-V ISA to GCC in 2017, and expects to continue to work with the RISC-V community to ensure the API is aligned to the final RVV 1.0 specification. Learn more about SiFive’s open-source contributions for RISC-V Vectors in our blog, here.

“The RISC-V Vector extension will enable new RISC-V based processor designs to accelerate many workloads, from AI to signal processing and scientific research,” said Chris Lattner, President of Platform Engineering, SiFive. “With the integration of support for intrinsics in popular compilers, the RISC-V community is enabled to create efficient, scalable hardware and software solutions to address modern computing challenges.”

SiFive Shield SoC-level Security
The SiFive Shield Hardware Cryptographic Accelerator (HCA) was introduced in the recent SiFive 20G1 release in July, enabling the acceleration of cryptographic functions used to securely boot an SoC, protect communications, and restrict access to the debug interface. The SiFive HCA IP block includes a 100% digital true random number generator (TRNG) that has successfully passed a conformance evaluation against the stringent NIST SP-800-90B recommendation for entropy sources used for random bit generation. Learn more about SiFive Shield HCA in our blog, here.

SiFive will release more updates to its RISC-V-based Core IP portfolio in October, with enhanced performance for the SiFive 7-Series range of U-, S-, and E-Series processor cores. These updates will improve performance in Artificial Intelligence workloads where data streaming performance is important, and be deployed to all customers using the award-winning SiFive Core Designer automatically.

About SiFive
SiFive is the leading provider of processor cores, accelerators, and SoC IP to create domain-specific architecture based on the free and open RISC-V instruction set architecture. SiFive offers scalable, configurable processor cores pre-integrated with security, trace, and debug features for workload-specific accelerator designs. Founded by the inventors of RISC-V, SiFive has 15 design centers worldwide and backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK hynix, Intel Capital, and Western Digital. For more information, please visit

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Media Contact

Hilary Livingston Castle
INK Communications