SiFive Intelligence
X300 Series

New in Second Generation 

• New RVA23 support 
• New RVV1.0 512-bit vector engine 
• New SSCI interface added alongside VCIX 
• New instructions and extensions 
• New improved memory subsystem 
• New memory latency tolerance
• New HW support of BF16 datatype 
• New vector crypto support
• Plus many other new features, enhancements and upgrades

RISC-V Vector extension supported

Up to 1024-bit VLEN Dual Vector ALU

512-bit DLEN

SiFive Intelligence Extensions for ML workloads

• New hardware accelerated Exponential Instructions
• Custom instructions to greatly accelerate Neural Network computation
• Optimized neural network libraries and Open XLA support

1024-bit vector register length processor

• Variable length operations, up to 512-bits of data per cycle
• Ideal balance of control logic and data parallel compute
• Decoupled Vector pipeline
• INT8 to INT64 integer data type
• BF16/FP16/FP32/FP64 floating point data type

Built on silicon-proven U7-Series core

• 64-bit RISC-V ISA
• 8-stage dual-issue in-order pipeline
• Coherent multi-core, Linux capable

High performance vector memory subsystem

• Shared L2 Cache architecture optimized for vector compute
• Dedicated uncached data movement port

Multi-core processor configuration, up to 4 cores

SSCI and VCIX specialized interfaces for close coupling with customer-designed external AI accelerators or other coprocessors 

• SiFive Scalar Coprocessor Interface (SSCI) to issue custom instructions to accelerators for optimum scheduling at lower latency  
• Vector Coprocessor Interface eXtensions (VCIX) allowing custom vector instructions to be executed on the accelerator at high bandwidth from the vector pipeline