SiFive; Empowering A New Era of Data Center Innovation

SiFive’s mission is to create the best computing solutions in the world so our customers can deliver differentiated, best-in-class products. We do this not only by building great intellectual property (IP), but also by driving the RISC-V ecosystem forward. The open standard RISC-V architecture is the last instruction set architecture (ISA) that will ever matter. It’s not often that you can be part of a computing revolution; especially one that is revolutionizing systems as we know them. SiFive helps spur innovation across a broad community while ensuring our customers benefit from the evolution of our high-performance IP, ecosystem, extensions, and tools.

RISC-V has firmly established itself in the embedded market across a diverse set of use cases. RISC-V is gaining traction in other markets including data centers, ADAS, consumer devices, space and automotive, as the main processor running the rich operating system and services. In these segments, the competition is x86 and Arm. The common trait across all these markets is the rapid change of system requirements which, in turns, creates an opportunity for disruption. SiFive understands the need to deliver solutions that are not just a few percentage points better than the offerings from the incumbents, but dramatically higher-performance, flexible solutions that our customers can tailor to specific applications. In this post, we’ll explore how SiFive’s latest data center offering meets the needs of demanding AI workloads.

At the core of strategy is the need to take a system level view. These systems require both highly capable general-purpose processing and optimizable-for-purpose AI performance. For the latter, SiFive has been delivering a set of Intelligence Processors that either couple tightly to a customers’ AI accelerator or, in the case of the newly announced XM Series, incorporates that functionality in addition to scalar and vector processing.

From the general-purpose processing perspective, SiFive launched the Performance P870-D Processor in August 2024. I find it extremely satisfying to see industry recognition of where the P870-D processor is positioned from a performance perspective, as shown on this slide from a presentation during the China RISC-V Summit in August 2024 by Semiinsights, an independent 3rd party company.

This is a block diagram of the P870-D. You will notice that there are a lot of elements outside the P870-D CPU core itself. We get strong, consistent feedback from customers of the need for suppliers to offer system elements beyond the CPU core itself. As a result, for all of our processor offerings across the performance spectrum, SiFive provides a compute solution that includes not only the core clusters, but also the uncore agents, the IOMMU Gen2, and WorldGuard for security. This complete solution improves system development cycles and costs and reduces program risk.

The P870-D is a 64-bit Out of Order (OoO) core that is 6 wide, enabling up to 50% more single threaded performance compared to our prior generation P670 core. The P870-D microarchitecture is focused on single threaded performance with low power consumption, while also optimizing area. In this respect, our first generation solutions are very competitive with later generations of the Neoverse N series.

The P870-D core cluster supports the AMBA CHI-E coherent interface, enabling customers to select any CHI-based third-party or customer-generated coherent network on-chip (NoC) solution. This support for a standards-based interface allows for easier integration into our customers’ existing fabric, offering core scalability which is critical for this segment. It is also core to our strategy of enabling chiplet based implementations as customers start to explore new SoC configurations that improve their flexibility to respond to new market opportunities.

The uncore agents enable the interrupt handling, MMU support, and trace/debug. The uncore agents offer a flexible routing to the clusters, enabling a variety of coherent interconnect topologies (supporting up to 256 cores).

WorldGuard is a fine-grain security model for isolated code execution and data protection. It provides SoC-level information control with advanced isolation control, based on multiple levels of privilege per world, and an unlimited number of worlds. In addition to the RISC-V Physical Memory Protection (PMP) that provides memory isolation for code and data manipulated by the CPU, WorldGuard expands hardware isolation to the whole SoC to protect caches, interconnects, arbitrary bus masters, memories, and peripherals. In summary, WorldGuard is a very practical, scalable solution for real-time SoC partitioning. The second generation IOMMU provides a split version of the IOMMU, offering a distributed architecture that supports up to 8 IOTLB to reduce bandwidth congestion. This feature extends the scalability of IO devices required for datacenters and networking. The second generation also has support for 57-bit virtual addresses for memory intensive workloads or multiple concurrent workloads.

Finally, P870-D’s reliability, availability and serviceability (RAS) provides protection for on-chip memories, processor architectural states (register files, control and status registers(CSR)), and key structures of the datapath including interconnect and shared cache controllers. The P870-D RAS solution provides frameworks to configure and report errors in a way that is compatible with the RISC-V standard specifications.

SiFive’s P870-D offering, augmented with SiFive’s Intelligence AI products, will be leading the charge in the transformation of data center architecture towards one that is open and standards-based. This approach allows customers to innovate faster and in a way that more efficiently tracks the unique requirements of their intended use case. A key catalyst contributing to this transformation is the Server Platform Specification authored by the RISC-V server task group. The specification defines a standardized set of hardware and software capabilities that system software (such as operating systems and hypervisors) can rely on being present in a RISC-V server platform. The end state will be a single binary OS image distribution model that ties together hardware (SoC), firmware, and security specifications. End customers continue to demand choice and what this enables is for companies to avoid lock-in to a particular RISC-V implementation since all suppliers that are pursuing this segment are engaged in creating solutions that conform to this specification.

SiFive is bringing all these elements together to open up new opportunities for AI innovation in data centers, with P870-D leading the charge. We look forward to sharing more details in the months ahead.