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In 2018, we hosted several RISC-V technology symposia in India, China and Israel. These events were very successful in fueling the growing momentum surrounding the RISC-V ISA in these countries. It turns out that these events were just the tip of the iceberg. In 2019, SiFive is greatly expanding its...

In 2018, we saw the rapid proliferation of the RISC-V architecture, with commercial deployments of SiFive Core IP in a broad range of applications ranging from wearables and edge devices to the enterprise core. Modern compute workloads are evolving rapidly and require the ability to scale performanc...

Published by SemiWiki. These were the closing words Yunsup Lee, CTO, SiFive used at one of the December RISC-V Summit Keynotes entitled ‘Opportunities and Challenges of Building Silicon in the Cloud’. Fired up was more the mood among the 1000+ attendees of the RISC-V Summit held at the Santa Clara C...

We are really excited to see Wave Computing announce the open MIPS ISA and R6 processor core. SiFive would like to congratulate and welcome MIPS to the open-source community with its MIPS Open Initiative. The addition of the MIPS 32 and 64-bit open ISA will provide more options freely available to S...

Hi everyone! I'm Nathaniel Graff, a software engineer here at SiFive, and I'm excited to tell you about the most recent release of Zephyr RTOS, version 1.13.0! Zephyr RTOS is a real-time operating system hosted by The Linux Foundation, featuring support for a myriad of different platforms, architect...

It's been another week, which means it's time to find another host for "Last Week in RISC-V". This week we're going to attempt a blog at riscv.org, which will hopefully be a good long-term home for this series of articles. As usual, you can find this week's entry on GitHub. glibc Floating-Point Tes...