In this blog, we’ll begin by introducing XNNPACK and exploring its current status on RISC-V platforms. Next, to bridge the technical gap for contributors, we will provide a step-by-step guide on integrating RVV-optimized microkernels into XNNPACK, using F32-GEMM (single-precision floating-point gene...

In June 2024, SiFive announced the 4th generation of its Essential Product line. Products from the Essential family are already deployed in billions of consumer and IoT products including smartphones, sensors, SSDs, FPGA platforms, surveillance cameras, smartwatches and more. This new release contai...

At the RISC-V Summit in North America this week, RISC-V International announced that the RVA23 Profile has been ratified. The fundamental objective behind RVA Profiles is to ensure software portability across hardware implementations.. This announcement reminded me of an important question that Krst...

Reflecting on how far we’ve come since SiFive launched the world’s first RISC-V development boards back in 2016, it’s clear we’ve been on an incredible journey together with the RISC-V software community. Those early boards, like the HiFive1, were game-changers—true ignitors for the entire RISC-V re...

SiFive’s mission is to create the best computing solutions in the world so our customers can deliver differentiated, best-in-class products. We do this not only by building great intellectual property (IP), but also by driving the RISC-V ecosystem forward. The open standard RISC-V architecture is t...