SiFive Vector Processing Solutions To Be Highlighted at Linley Spring Processor Conference 2021

Tremendous progress has been made in the last year bringing RISC-V vector (RVV) extensions to market in both hardware implementations and supporting compiler technologies.

SiFive has gone a step further with the inclusion of new vector operations specifically tuned for the acceleration of machine learning operations. These new instructions, integrated with a multicore, Linux-capable, dual-issue microarchitecture, with up to 512b wide vectors, and bundled with TensorFlow Lite support, are well-suited for high-performance, low-power inference applications.

View more about SiFive Intelligence vector processing software and hardware here.

At the upcoming Linley Spring Processor Conference 2021, Chris Lattner, SiFive’s President of Engineering and Product, will be presenting a technical update on SiFive’s vector processing solutions titled: “Enhancing RISC-V Vector Extensions to Accelerate Performance on ML Workloads.” In his talk, he will demonstrate how SiFive’s integrated software and hardware solution addresses low-power inference applications. Prior to SiFive, Chris led development teams (including TensorFlow infrastructure, MLIR, and other AI work) at Apple, Tesla and Google, and he is the creator of Clang, the compiler front end, as well as LLVM, the compiler infrastructure open source project.

Announced SiFive Intelligence vector processing Core IP includes products capable of supporting full-featured operating systems such as Linux.

We look forward to seeing you at the Linley event and sharing with you the updates to our vector processing solution.

More on SiFive RVV support:

• SiFive collaborates to support RVV Intrinsics in popular GCC and LLVM compilers (blog)
• Extending AI SoC design possibilities through Linux-capable vector processors (video)
• Introduction to SiFive Intelligence RVV Core IP (video)