来自 RISC-V 专家的最新洞察与深度技术解析

This one-hour webinar is for Embedded Developers who are interested in learning
more about the RISC-V architecture.  It covers areas such as the Register File,
Instruction Types, Modes, Interrupts, and Control and Status Registers. Prior
knowledge of RISC-V is not necessary, but having a basic understanding of
Computer Architecture is beneficial.

Check out the webinar recording [here](https://info.sifive.com/risc-v-webinar)!



Developer enablement updates for RISC-V infrastructure: Red Hat RHEL on HiFive Premier P550, NVIDIA CUDA port, RVA23 ratification, Canonical Ubuntu support, and RISE Project advancements.

![Premier P550 Board](https://images.prismic.io/sifive/aJqr6aTt2nPbaMH9_SiFive_NVIDIA-CUDA_Blog_1000x500.jpg?auto=format,compress)
**By Ian Ferguson, V.P. of Business Development, SiFive** 

When I joined SiFive in early 2024, the initial focus (which has since broadened) was to explore how best to drive adoption of SiFive’s [RISC-V technology](https://www.sifive.com/about/risc-v-history) into system-on-chip components targeting [data center use cases](https://www.sifive.com/solutions/data-center). Efforts to introduce new technologies, and to displace long-term incumbents, are not initiatives that succeed in just a few quarters. These programs take years to execute. I speak from experience: in early 2008, a few colleagues and I, described internally as “rogues” (though we preferred “visionaries”), started the initiative to drive Arm into the server market.

Upon arriving at SiFive, it was clear that our CPU roadmap would, over time, catch up with the single-thread performance capabilities of products from incumbent suppliers. But three other areas also needed to be addressed to truly open this market to a broader set of customers, beyond just one or two early [innovators](https://medium.com/@samuelvandeth/crossing-the-chasm-162802d1cf27).

The first area I’ll explore in this blog post is enabling the software developer community. I’ll leave the other two as a mystery (for now) and return to them in future posts later this year.

**Three Numbers for You:**

**90**

**4**

**12,800**


What do these numbers mean? Today, projections show that NVIDIA “owns” 90% of GPU-based neural network training. They boast a developer base exceeding four million people. And, on average, 12,800 lines of code are added, modified, or deleted in the Linux kernel each day.

A few folks have posited that "hardware is cool again," but fundamentally, without strong software support, the effort for companies to adopt new hardware technologies is simply too great.

In May, [Red Hat announced](https://www.redhat.com/en/blog/red-hat-partners-with-sifive-for-risc-v-developer-preview-for-red-hat-enterprise-linux-10) the release of a developer edition of Red Hat Enterprise Linux (RHEL) for use on SiFive’s latest [RISC-V developer board, the HiFive Premier P550](https://www.sifive.com/boards/hifive-premier-p550). Alongside this, they also made RISC-V source code available for the [CentOS community](https://blog.centos.org/2025/05/initial-centos-support-for-risc-v/).

Then in July 2025, NVIDIA announced it is porting CUDA to RISC-V, using the HiFive Premier P550 as the starting point for this work. While no timeline was shared for when the code will be available, the announcement has already generated significant interest across the press, customer base, and competitor landscape.

At this point, I can’t expand beyond what’s already in the public domain. But there's an excellent analysis by **Joe Byrne** posted [here](https://xpu.pub/2025/07/23/cuda-risc-v/) that gives helpful context. As Joe writes:

“NVIDIA is making RISC-V a supported architecture, alongside Arm and x86—which means that, once the code is available, companies will be able to select a RISC-V CPU to be coupled alongside a NVIDIA GPGPU.”

RISC-V International also just released a [blog](https://riscv.org/blog/2025/08/nvidia-cuda-rva23/) based on a discussion with Frans Sijstermans, the NVIDIA executive who revealed the news at the [RISC-V Summit China](https://riscv-summit.com/en/).

**Common Themes from Red Hat and NVIDIA**

I see three common threads across Red Hat’s and NVIDIA’s announcements:

**Future-Readiness:** Both companies are preparing for a future where RISC-V server hardware is widely deployed. They want to be ready for that reality.

**Platform of Choice:** Both are basing their initial work on the [HiFive Premier P550 board](https://www.sifive.com/boards/hifive-premier-p550). I believe that’s due to its high performance relative to other RISC-V boards, its stability, and the excellent work our engineering team is doing to upstream open source code—plus the performance and expansion capabilities of the hardware. Having this powerful capability in silicon is enabling many developers to get “hands-on” with RISC-V in new ways.

**RVA23 Milestone:** The ratification of the [RVA23 profile](https://riscv.org/riscv-news/2024/10/risc-v-announces-ratification-of-the-rva23-profile-standard/) has had a galvanizing effect. Large ecosystem players want to target platforms that are supported by multiple vendors with a consistent processor architecture. A common instruction set that software can count on is key to making that possible.

It would be remiss not to recognize the pioneering work Canonical has done in the RISC-V ecosystem—making Ubuntu a first-class citizen for RISC-V.

The combined investments of these industry heavyweights, along with support from many companies participating in the [RISE Project](https://riseproject.dev/), are bringing us closer to a reality where customers can choose among three processor architectures. Barriers for system builders, software developers, and component vendors are being removed—almost daily.

RISC-V is unique in its openness. Vendors can build chips for narrow, highly specialized vertical markets. NVIDIA clearly sees an opportunity here to extend CUDA into entirely new domains—something that would be much harder to do with other commercial ISAs designed to serve broad, generic markets.

The power of CUDA combined with the unlimited future of RISC-V is truly exciting.

SiFive recently celebrated our [**ten-year anniversary**](https://www.sifive.com/blog/sifive-celebrates-10-years-as-your-trusted-partner), and we continue to push the boundaries of what’s possible with RISC-V. As always, we want to hear from you—your ideas, your innovations, and your challenges.

We’ll all come together at the RISC-V Summit in Santa Clara this October, where I’m looking forward to some great presentations and discussions. Let’s use that as a platform to expand the conversation and accelerate momentum even further.

Ultimately, it’s now up to the RISC-V community to prove NVIDIA right.

Discover how SiFive is advancing RISC-V for Infrastructure, with Red Hat and NVIDIA enabling powerful software support, the HiFive Premier P550 platform, and a rapidly growing developer ecosystem.

RISC-V for Infrastructure: For Now, It’s All About the Developer

SiFive_NVIDIA-CUDA_Blog_1000x500.jpg

![ten year logo](https://images.prismic.io/sifive/aIKcBlGsbswqTO20_SiFive_10years_Blog_Social_1920x1920-v1.2.jpg?auto=format,compress)

SiFive 成立的初衷有一个简单却远大的目标：让 RISC-V 走向全球，推动定制芯片设计迈向更加开放、人人可及的未来。十年之后，我们很荣幸能在 RISC-V 生态的蓬勃发展中扮演重要角色，且我们的成就更是离不开全球社区的支持、合作与信任。

**从实验室到‌行业领袖**

我们已取得了超过 400 项设计胜利、市场上已有超过 100 亿颗采用 SiFive 技术的核心，这些里程碑让我们引以为豪。但我们知道这些结果只是一个更大故事的一部分。
RISC-V 的发展远超最初的预期。我们感到欣慰的是，SiFive 不仅推动了 RISC-V 技术的进步，也积极参与并支持促使开放标准蓬勃发展的协作环境。我们的员工共同塑造 SiFive 勇于创新、协作共赢、专注解决客户挑战的企业文化。

**应对快速变化**

过去十年，行业经历翻天覆地的变化，尤其是人工智能的迅速崛起与汽车领域的转型升级。我们与合作伙伴及客户紧密合作，不断优化 IP 产品，以应对新的挑战：助力和支持 AI 加速，提供面向汽车的分布式区域架构，并交付高效能、低功耗的解决方案，以满足新兴市场的需求。
从数据中心到边缘计算，从航空航天到物联网，我们有幸与各行业的创新企业携手合作。全球前十大半导体公司中已有八家在他们的产品中采用 SiFive IP，且每一次合作都让我们持续学习并共同成长。全球七大超级科技公司（Magnificent 7）均已启动 RISC-V 项目，我们也很自豪能与其中大多数公司开展合作。

**过去十年的精彩瞬间**

SiFive 的成长离不开团队的专注投入和 RISC-V 社区的紧密协作。以下信息图展示了部分令我们自豪的发展里程碑。

![10 Year Infographic](https://images.prismic.io/sifive/aJC5nKTt2nPbZ0aZ_SiFive-10Years-Infographic-Final-CN.jpg?auto=format,compress)

在此期间，我们持续为 RISC-V International 和开放软件生态做出贡献，从 Android、IREE、WorldGuard 到 RISE Project，我们始终坚信开放必将加速创新。

**展望未来：携手共绘蓝图**

步入第二个十年，我们对未来充满期待。不仅是对 SiFive 本身，更是对整个 RISC-V 生态。各类应用场景中的机遇持续出现，我们将一如既往地在每个阶段支持合作伙伴。不论何种应用，我们都以成为值得信赖的合作伙伴为目标，这个使命贯穿公司每一个环节。

**感谢有您**

这个里程碑不只属于 SiFive，更属于所有与 SiFive 携手前行的工程师、开发者、研究人员、客户、投资者及拥护者。正因为大家共同相信，更加开放的计算方式不仅可行，而且势在必行，SiFive 才能走到今天。那些早期看到潜力并选择信任我们的采用者，如今已与全球最大的半导体与超大规模计算企业并肩前行，引领我们向前。

衷心感谢在过去十年支持 SiFive 的每一位朋友。是你们的信任与合作，使我们每天都倍感激励。让我们共同迎接下一个十年的创新之旅!

Screenshot 2025-07-22 at 9.16.03 PM.png

SiFive 庆祝十周年：感恩同行，携手共进


**Pavel Chupin, Senior Director of AI Software, SiFive**

![Birdseye view](https://images.prismic.io/sifive/aGW3H3fc4bHWi-0e_SiFive_BEVFormer_Blog_1000x500.jpg?auto=format,compress)

SiFive 很高兴地宣布：BEVFormer 模型已成功部署在 SiFive 的 Intelligence XM IP 上，这是基于 RISC-V 的早期可用 AI 加速解决方案。此成果凸显了开放标准硬件处理自动驾驶复杂感知工作负载的潜力。

**BEVFormer：成熟模型，新的挑战**

BEVFormer 于 2022 年发布，是一成熟的基于 Transformer 的 Bird’s Eye View (BEV) 感知模型，对自动驾驶至关重要。它将来自六个 900×1600 分辨率摄像头的输入转换为 200×200 的 BEV 表征，从而支持稳健的 3D 目标检测、空间推理及时序信息融合。

![BEVFormer Image](https://images.prismic.io/sifive/aGWr4Xfc4bHWi-xL_Slide1.jpeg?auto=format,compress)

虽然 BEVFormer 本身并不新颖，但真正的突破在于将这复杂模型成功移植到 SiFive Intelligence XM 平台 —— 一个新兴的、可用的 RISC-V 架构上。这次部署展示该平台应对高要求 AI 工作负载的能力，为未来汽车创新奠定基础。

**RISC-V 与 SiFive Intelligence XM IP 的优势**

汽车 AI 需要高性能、可定制、且具备能效优势的计算平台，以支持生命周期长的系统。传统专有处理器在灵活性方面往往存在不足，而 RISC-V 开放标准指令集架构（ISA）通过允许为特定工作负载（如神经网络推理和实时控制）量身定制处理器设计，解决了上述痛点。

[SiFive Intelligence XM](https://www.sifive.com/cores/intelligence-xm-series) 平台目前仍处于早期可用阶段，基于此架构构建多核设计，包含四个 X 系列内核（每个内核配备 1024 位 RISC-V 矢量单元）及一个矩阵引擎，用于高效执行矩阵运算。其高度集成的架构最大限度地降低延迟，并消除异构系统中常见的回退性能损失。这使得 BEVFormer 的各种模块：卷积层、可变专注度机制、标量操作，能在同一个二进制文件中无缝执行，简化开发流程并提升性能。
![SiFive XM Series](https://images.prismic.io/sifive/aGbXN3fc4bHWjCBE_Slide1.jpeg?auto=format,compress)
**攻克部署难点**

在 XM 系列 IP 上运行 BEVFormer 是一项复杂工程，团队需针对多项技术挑战提出创新解决方案。借助由 IREE 驱动的 SiFive AI/ML 参考软件栈，团队对模型进行了一系列优化以适配 XM 平台。关键步骤包括：

- 模型转换：解决 PyTorch 1.9.1 与 OpenMMLab 的兼容性问题，将 BEVFormer 转换为 ONNX 格式，并利用 IREE 的 iree-import-onnx 工具转为 MLIR。
- 自定义算子支持：将关键算子（如 Modulated_Deform_Conv2D 和 Multi_Scale_Deformable_Attention）实现为高效的微内核，充分利用 RISC-V 矢量扩展（RVV）指令提升性能。
- CUDA 到 RISC-V 的移植：将 CUDA 内核转换为可移植的 C/C++ 及 RVV 代码，借助大语言模型（LLM）辅助原型开发，节省工程人力。
- 矩阵引擎优化：通过 IREE 的 mmt4d 框架，将矩阵密集型运算（如矩阵乘）映射到矩阵引擎，实现硬件加速。

整个流程在 nuScenes 数据集上通过 XM 平台的 QEMU 仿真进行验证，准确率与 PyTorch 基线完全一致。可视化输出进一步验证了模型在生成 BEV 表示时的高精度，证明了该平台的强大能力。

**未来的基石**

这项成果的意义并不在于 BEVFormer 模型本身的新颖性，而在于通过 SiFive AI/ML 参考软件栈，证明 SiFive Intelligence XM 平台可以胜任复杂 AI 工作负载。成功部署像 BEVFormer 这样成熟的模型，表明 RISC-V 有能力与传统汽车计算解决方案竞争，同时具备更大的灵活性与可定制性。由 IREE 驱动的 SiFive AI/ML 参考软件栈也为后续更多 AI/ML 模型的尝试提供了可能，开发者可基于已有的开源技术进行探索和复用。

SiFive 团队正在持续通过内核调优和代码生成优化性能。随着 RISC-V 在汽车 AI 领域的持续发展，这一里程碑将有助于 SiFive 平台成为可扩展、开放标准解决方案的新标杆。

**深入探索，加入我们**

您还可以在 GitHub 上查看 BEVFormer 的完整代码库。
有兴趣评估 SiFive Intelligence XM 平台，或在汽车 AI 领域与我们合作吗？SiFive 拥有业界最丰富的汽车 RISC-V 解决方案组合。欢迎[联系我们](https://www.sifive.com/contact-sales)，一起推动自动驾驶的未来发展！


SiFive_BEVFormer_Blog_1000x500.jpg

汽车 AI 新突破：SiFive XM 平台成功支持 BEVFormer 自动驾驶模型

SiFive and Red Hat deliver a developer preview of RHEL 10 on the HiFive Premier P550, marking a major step for RISC-V for Infrastructure and expanding enterprise software support.

**Ian Ferguson, VP of Vertical Markets**

I have worked with processor technology for well over 30 years. It was clear to me from the first product I worked with ([88k](https://en.wikipedia.org/wiki/Motorola_88000) from Motorola Semiconductor) that hardware was unable to make an impact on an industry without relevant, effective software support.

From my perspective, while is fair to indicate that the era of AI is reducing the ties of software to underlying hardware...or [“hardware is eating the world”](https://www.deloitte.com/ce/en/services/consulting/perspectives/hardware-is-eating-the-world.html) as some care to describe it….there is still a critical need to deliver complete, stable foundational software in order for hardware technology to flourish in a specific market and application area.

Today, [SiFive announced a collaboration with Red Hat](https://www.sifive.com/press/sifive-collaborates-with-red-hat-support-enterprise-linux-risc-v) to deliver a developer preview of [Red Hat Enterprise Linux (RHEL) 10](https://www.redhat.com/en/about/press-releases/red-hat-introduces-rhel-10) for RISC-V. The developer preview is available exclusively on our [HiFive Premier™ P550 board](https://www.sifive.com/boards/hifive-premier-p550). In essence, a Developer Preview is a way for Red Hat to engage with its community and gather valuable feedback on upcoming features before they are finalized and released as part of a supported product. This Developer Preview enables early adopters and integrators to experiment with new features and provide feedback to Red Hat. The beta of [Red Hat Enterprise Linux 10](https://www.redhat.com/en/blog/red-hat-enterprise-linux-10-beta-now-available) was released in December 2024.

With RISC-V starting with an open standards approach, the primary way of maturing a new ISA is by having a development platform that hardware and software developers can use.  As a participant in the open-source communities that strive to enable solutions to customer problems and business needs, Red Hat understands that some members of the ecosystem will naturally gravitate to Fedora and CentOS STREAM and the rapid innovation they deliver, while others are interested in a slightly slower pace for other parts of the ecosystem.

I feel that Red Hat’s decision to start their hardware integration with SiFive sends a clear message about the quality, performance and technical support that this board provides. That said, it is also important to give a shout out to the significant impact of the open-source community, particularly those invested in the [RISE Project](https://riseproject.dev), for their work to continue to port, optimize and upstream the critical pieces of RISC-V enabling code that are making this market-disrupting milestone a reality. 

This highly anticipated software is immediately available. Red Hat staff is showcasing the software running on the P550 at this week’s Red Hat Summit in Boston where customers, partners and analysts can view a hands-on demonstration. It is a non-trivial decision to embark on a path to support a new processor architecture, and I view this as an important commitment that supports the growing importance and acceptance of RISC-V for high-performance use cases.

In many ways, this is not the end of the journey, it is the start. There is much foundational work still to be done by SiFive, Red Hat, other RISC-V members as well as in the broader open-source community.  This work will ultimately enable RISC-V to compete on a level playing field with incumbent architectures in the Enterprise server market. Today’s announcement with Red Hat is a massive step forward and the SiFive team is eager to continue to contribute in doing its part on the journey ahead.

**May 22 update**

I mentioned above about the linkages between Red Hat software and other distributions. Within a day of the announcement of our collaboration with Red Hat, there were three important updates: 

1) A [blog post](https://blog.centos.org/2025/05/initial-centos-support-for-risc-v/) as issued on the CentOS community page outlining plans for RISC-V support

2) Rocky Linux [announced](https://rockylinux.org/news/rockylinux-support-for-riscv) intent to add RISC-V images to their distribution

3) On the public Fedora channel, Alma also claimed: "FWIW AlmaLinux will be supporting it with 10 too, we're just not making flashy blog posts about it."

All of this activity will provide more options for developers, inspiring innovation and creating highly differentiated platforms for the end customer base.




Red Hat Brings Their Enterprise Linux On SiFive Hardware

SiFive_redhat-launch_Blog_1000x500.jpg

Red Hat Brings Their Enterprise Linux On SiFive Hardware!

十五年前，一个大胆的构想在大学实验室中诞生：如果芯片设计能够变得更加开放，让更多人能够参与和创新，会带来怎样的变化？如果一种现代、开放标准的指令集架构（ISA）能够赋能全球工程师和创新者，摆脱专有许可的束缚，会怎样？这个想法孕育出了 RISC-V，并迅速发展为一场重塑计算未来的全球浪潮。

## 起源：加州大学伯克利分校的一项创新构想
 
RISC-V 的故事始于 2010 年，加州大学伯克利分校的 Parallel Computing Laboratory (Par Lab)，在 Krste Asanović 教授和研究生 Andrew Waterman、Yunsup Lee（后来共同创办了 SiFive）的带领下，RISC-V 源于迫切的需求和远大的愿景。在“RISC 之父”David Patterson 的支持下，他们决定打造一种简单、灵活、最重要的是“开放”的指令集架构。

“我们希望将 RISC-V 打造为所有计算领域的标准指令集架构。” ——SiFive 联合创始人兼首席工程师 Andrew Waterman

他们将其命名为 RISC-V（发音为“RISK FIVE”），代表第五代 RISC ISA。它的不同之处在于：RISC-V 是模块化的，从零开始设计，避免了传统架构的历史包袱和专有复杂性。这种具有历史意义的革命性新 ISA 可以从低功耗嵌入式设备扩展到高性能数据中心工作负载。

## 开放硬件的崛起

到 2015 年，RISC-V 已超越学术范畴。同年，RISC-V 基金会（现为 RISC-V International，简称 RVI）成立，作为独立机构推动整个计算生态中的 ISA 发展。RVI 总部设在瑞士，象征其中立和独立的全球开放标准地位。尽管 RVI 是一个独立的标准机构，Krste 和 Andrew 仍担任重要顾问角色，并持续投入塑造 RISC-V 的未来规范、架构和愿景。

SiFive 已向 RISC-V 捐赠了多项技术，包括 WorldGuard security IP、以及用于 AI 计算的向量点积和向量矩阵扩展。

RISC-V International 现已拥有来自 70 个国家、超过 4,500 名成员，其中涵盖初创公司和全球科技巨头。

“我们相信，RISC-V 实现了芯片设计的开放与普及，释放了前所未有的创造力与竞争力，这在传统专有模式下是无法实现的。” ——SiFive 联合创始人兼首席技术官 Yunsup Lee

这种开放性推动了空前的创新。RISC-V 现已应用于数十亿台设备，覆盖汽车、航天、移动、嵌入式系统及超大规模数据中心等行业。几乎所有科技巨头（包括：苹果、微软、亚马逊、谷歌、Meta、英伟达和特斯拉）都已不同程度地采用 RISC-V。

“AI 是推动 RISC-V 加速应用的关键动力之一。RISC-V 的可定制性和高效性，使其成为新一代 AI 创新的理想基础。” ——SiFive 联合创始人兼首席架构师 Krste Asanović

## SiFive：引领 RISC-V 的创新浪潮
 
看到 RISC-V 的潜力，三位发明人于 2015 年联合创办了 SiFive——首家专注于开发基于 [RISC-V 的处理器 IP 的公司](https://www.sifive.cn/risc-v-core-ip)（芯片厂商可据此构建 RISC-V 芯片）。SiFive 现已成为 RISC-V 创新的领导者，获得超过 400 个 design wins，IP 已被部署于超过 20 亿台设备中。

自 2020 年 CEO Patrick Little 上任以来，SiFive 聚焦于汽车和人工智能等高增长市场，同时率先推出可扩展的 IP 解决方案，涵盖超低功耗嵌入式内核、高性能超标量处理器、高性能向量和矩阵处理器。

“RISC-V 的起源很低调：2010 年，我们最初的目标仅仅是为伯克利的教学和研究设计一个简洁的指令集架构。” ——SiFive 联合创始人兼首席工程师 Andrew Waterman

## 展望未来：RISC-V 的下一个 15 年
 
RISC-V 不再是“是否”的问题，而是“何时”的问题。分析师和业内人士普遍预测 RISC-V 将逐步取代传统 ISA，成为计算领域的默认标准。

“目前虽有三大主流 ISA，但我相信未来 15 年内，RISC-V 将成为大多数主要计算市场的主导 ISA。” ——Yunsup Lee

AI 和嵌入式系统是驱动这一增长的两大关键因素。在嵌入式领域，RISC-V 的能效与可扩展性使其成为首选；而在 AI 领域，其针对特定工作负载（尤其是矩阵和向量运算）定制硬件的能力正吸引着众多大型企业。

“向量计算正在成为各个市场领域的基础技术。我相信在未来 15 年内，随着并行计算的持续增长，RISC-V 将稳固地成为该领域的首选架构。” ——Krste Asanović

AI 是全新的领域，几乎所有硬件设计都需要定制。RISC-V 作为系统基础，允许客户聚焦于自身最擅长的领域再通过专属扩展发挥优势。RISC-V 正被集成到数据中心的众多领域以及用于 AI 计算的边缘设备中。这为 SiFive 和 RISC-V 生态系创造了巨大的机遇。

“我们起初是现状的替代者，如今我们在多个领域已具备技术领先优势。我们的客户借助定制化与灵活性，加快上市速度——而我们则交付可扩展的真实软件兼容性。” ——Andrew Waterman

第三个推动因素是企业希望摆脱供应商锁定的强烈需求。媒体普遍猜测，某些主要 ISA 供应商可能会自造芯片，与客户竞争。众多公司正密切关注此事，几乎每一家科技巨头都已启动 RISC-V 项目，以应对这个可能性。


## 超越架构的 RISC-V 愿景
 
RISC-V 不仅是一种 ISA，它更是一个愿景。它已成为“工程自由、协作创新”的象征。从教室到数据中心，RISC-V 正为新一代计算奠定基础——一个由创新主导、而非专有壁垒主导的时代。

正如 Krste 所说： “我们与之交流的每个人都在将项目迁移至 RISC-V。我认为，整个计算生态最终将向 RISC-V 收敛，一切只是迟早的事。”

想了解更多关于 RISC-V 的历史吗？
访问 [RISC-V 的历史](https://www.sifive.cn/about/risc-v-history)页面，探索 RISC-V 从大学项目到全球标准的历程。

十五年前，一个大胆的构想在大学实验室中诞生：如果芯片设计能够变得更加开放，让更多人能够参与和创新，会带来怎样的变化？如果一种现代、开放标准的指令集架构（ISA）能够赋能全球工程师和创新者，摆脱专有许可的束缚，会怎样？这个想法孕育出了 RISC-V，并迅速发展为一场重塑计算未来的全球浪潮。

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