Accelerating the Future of RISC-V

The freedom of RISC-V enables a bright future for SiFive

What a time to be in the Semiconductors and CPU industry! As an industry, we are experiencing a perfect storm. With the rise of machine learning, cloud computing, and autonomous driving; the need for advancement in computing has never been greater. This is happening at a time when Moore’s law has considerably slowed and dennard scaling has come to an end. Architectural innovation is required to break out of the current logjam, but the closed nature of proprietary ISAs that have dominated our industry for three decades are unwieldy and unsuitable for application-specific computing needs going forward.

"Moving forward, the logical path is to add extensions to the basic instruction sets on microprocessors for application domains"

• David Patterson (Computing pioneer, Turing award winner, and father of RISC architecture), speaking to CACM

The open nature of the RISC-V ISA coupled with SiFive’s best-in-class design methodology makes it an ideal place to build the next computer. SiFive is already the premier supplier of RISC-V CPU to the industry, with 300+ design wins, 100+ customers, and 8 out of the top 10 semiconductor companies and I’m super excited to have the opportunity to be a part of this revolution.

Today I’m thrilled and proud to announce that I have joined SiFive to lead the Engineering team to build the best-in-class processor IPs that will be at the heart of future computing platforms.

I’ve been lucky to be associated with both of the major computing platforms of the last 25 years. First at AMD, where I worked on their highest-performance x86 CPUs, and then at Apple, where I led the implementation of CPU IP in the A5X through A13 SoCs. It was humbling to have the opportunity to lead the first implementation of the 64-bit mobile CPU (cyclone) that changed the world. During this journey, I pioneered many low power design techniques and we hired & built one of the best CPU design teams. Fitting desktop CPU performance into a phone power envelope required re-thinking everything from architecture to floorplan to clocking to std cell library choices and novel ways to visualize power so the entire team could focus on power-first design.

At SiFive we’re building best-in-class CPUs with a full range of performance options that give our customers more choice & flexibility. I’m looking forward to scaling the team to achieve new heights in performance and power efficiency. To learn more about our capabilities and products, please come see me at the RISC-V Summit, Dec 6-8.